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Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags

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result.  This allows us to compile:

void *test12(long count) {
      return new int[count];
}

into:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	movq	$-1, %rdi
	cmovnoq	%rax, %rdi
	jmp	__Znam                  ## TAILCALL

instead of:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	seto	%cl
	testb	%cl, %cl
	movq	$-1, %rdi
	cmoveq	%rax, %rdi
	jmp	__Znam

Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-05 07:49:54 +00:00
parent b20e0b1fdd
commit 9637d5b22e
2 changed files with 25 additions and 0 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7207,6 +7207,9 @@ static bool isX86LogicalCmp(SDValue Op) {
Opc == X86ISD::AND))
return true;
if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
return true;
return false;
}

22
test/CodeGen/X86/select.ll
View File

@ -178,4 +178,26 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
}
declare noalias i8* @_Znam(i64) noredzone
define noalias i8* @test12(i64 %count) nounwind ssp noredzone {
entry:
%A = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %count, i64 4)
%B = extractvalue { i64, i1 } %A, 1
%C = extractvalue { i64, i1 } %A, 0
%D = select i1 %B, i64 -1, i64 %C
%call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
ret i8* %call
; CHECK: test12:
; CHECK: mulq
; CHECK: movq $-1, %rdi
; CHECK: cmovnoq %rax, %rdi
; CHECK: jmp __Znam
}
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone