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Remove tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -673,7 +673,7 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
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// Inherit live-ins from the successor
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for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
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E = Succ->livein_end(); I != E; ++I)
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E = Succ->livein_end(); I != E; ++I)
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NMBB->addLiveIn(*I);
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// Update LiveVariables.
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@ -100,7 +100,7 @@ namespace {
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void ExitScope(MachineBasicBlock *MBB);
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bool ProcessBlock(MachineBasicBlock *MBB);
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void ExitScopeIfDone(MachineDomTreeNode *Node,
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DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
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DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
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bool PerformCSE(MachineDomTreeNode *Node);
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};
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} // end anonymous namespace
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@ -1057,8 +1057,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
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I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
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++I)
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if (MInfo.regsKilled.count(*I)) {
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report("Virtual register killed in block, but needed live out.", MFI);
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*OS << "Virtual register " << PrintReg(*I)
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report("Virtual register killed in block, but needed live out.", MFI);
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*OS << "Virtual register " << PrintReg(*I)
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<< " is used after the block.\n";
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}
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}
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@ -1639,7 +1639,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
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SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
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return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
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N1.getOperand(0));
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N1.getOperand(0));
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}
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// fold ((A+(B+or-C))-B) -> A+or-C
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if (N0.getOpcode() == ISD::ADD &&
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@ -2269,9 +2269,9 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
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// A divide for UMULO will be faster than a function call. Select to
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// make sure we aren't using 0.
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SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
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RHS, DAG.getConstant(0, VT), ISD::SETNE);
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RHS, DAG.getConstant(0, VT), ISD::SETNE);
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SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
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DAG.getConstant(1, VT), RHS);
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DAG.getConstant(1, VT), RHS);
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SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
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SDValue Overflow;
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Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
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@ -2292,8 +2292,8 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
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SDValue Temp = DAG.CreateStackTemporary(PtrVT);
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// Temporary for the overflow value, default it to zero.
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SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
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DAG.getConstant(0, PtrVT), Temp,
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MachinePointerInfo(), false, false, 0);
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DAG.getConstant(0, PtrVT), Temp,
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MachinePointerInfo(), false, false, 0);
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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@ -2317,15 +2317,15 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
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SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
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TargetLowering::
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CallLoweringInfo CLI(Chain, RetTy, true, false, false, false,
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0, TLI.getLibcallCallingConv(LC),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Func, Args, DAG, dl);
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0, TLI.getLibcallCallingConv(LC),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Func, Args, DAG, dl);
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std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
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SplitInteger(CallInfo.first, Lo, Hi);
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SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
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MachinePointerInfo(), false, false, false, 0);
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MachinePointerInfo(), false, false, false, 0);
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SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
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DAG.getConstant(0, PtrVT),
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ISD::SETNE);
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@ -5207,9 +5207,9 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
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Outs, TLI);
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bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
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DAG.getMachineFunction(),
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FTy->isVarArg(), Outs,
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FTy->getContext());
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DAG.getMachineFunction(),
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FTy->isVarArg(), Outs,
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FTy->getContext());
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SDValue DemoteStackSlot;
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int DemoteStackIdx = -100;
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@ -5976,11 +5976,11 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
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if (OpInfo.ConstraintVT != Input.ConstraintVT) {
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std::pair<unsigned, const TargetRegisterClass*> MatchRC =
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TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
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std::pair<unsigned, const TargetRegisterClass*> MatchRC =
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TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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std::pair<unsigned, const TargetRegisterClass*> InputRC =
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TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
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std::pair<unsigned, const TargetRegisterClass*> InputRC =
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TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
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Input.ConstraintVT);
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if ((OpInfo.ConstraintVT.isInteger() !=
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Input.ConstraintVT.isInteger()) ||
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@ -6770,7 +6770,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
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// Note down frame index.
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if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
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dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
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FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
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SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
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@ -3033,10 +3033,12 @@ TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
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AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
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if (OpInfo.ConstraintVT != Input.ConstraintVT) {
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std::pair<unsigned, const TargetRegisterClass*> MatchRC =
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getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
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std::pair<unsigned, const TargetRegisterClass*> InputRC =
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getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
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std::pair<unsigned, const TargetRegisterClass*> MatchRC =
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getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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std::pair<unsigned, const TargetRegisterClass*> InputRC =
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getRegForInlineAsmConstraint(Input.ConstraintCode,
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Input.ConstraintVT);
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if ((OpInfo.ConstraintVT.isInteger() !=
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Input.ConstraintVT.isInteger()) ||
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(MatchRC.second != InputRC.second)) {
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@ -93,8 +93,9 @@ getELFKindForNamedSection(StringRef Name, SectionKind K) {
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// N.B.: The defaults used in here are no the same ones used in MC.
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// We follow gcc, MC follows gas. For example, given ".section .eh_frame",
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// both gas and MC will produce a section with no flags. Given
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// section(".eh_frame") gcc will produce
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// .section .eh_frame,"a",@progbits
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// section(".eh_frame") gcc will produce:
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//
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// .section .eh_frame,"a",@progbits
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if (Name.empty() || Name[0] != '.') return K;
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// Some lame default implementation based on some magic section names.
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@ -138,7 +138,7 @@ void IntelJITEventListener::NotifyFunctionEmitted(
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// the first instruction that has one
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if (FunctionMessage.source_file_name == 0) {
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MDNode *scope = I->Loc.getScope(
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Details.MF->getFunction()->getContext());
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Details.MF->getFunction()->getContext());
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FunctionMessage.source_file_name = const_cast<char*>(
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Filenames.getFullPath(scope));
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}
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@ -152,7 +152,7 @@ void IntelJITEventListener::NotifyFunctionEmitted(
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}
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Wrapper.iJIT_NotifyEvent(iJVM_EVENT_TYPE_METHOD_LOAD_FINISHED,
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&FunctionMessage);
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&FunctionMessage);
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MethodIDs[FnStart] = FunctionMessage.method_id;
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}
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@ -2998,7 +2998,7 @@ bool GenericAsmParser::ParseDirectiveCFISameValue(StringRef IDVal,
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/// ParseDirectiveCFIRestore
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/// ::= .cfi_restore register
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bool GenericAsmParser::ParseDirectiveCFIRestore(StringRef IDVal,
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SMLoc DirectiveLoc) {
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SMLoc DirectiveLoc) {
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int64_t Register = 0;
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if (ParseRegisterOrRegisterNumber(Register, DirectiveLoc))
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return true;
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@ -3011,7 +3011,7 @@ bool GenericAsmParser::ParseDirectiveCFIRestore(StringRef IDVal,
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/// ParseDirectiveCFIEscape
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/// ::= .cfi_escape expression[,...]
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bool GenericAsmParser::ParseDirectiveCFIEscape(StringRef IDVal,
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SMLoc DirectiveLoc) {
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SMLoc DirectiveLoc) {
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std::string Values;
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int64_t CurrValue;
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if (getParser().ParseAbsoluteExpression(CurrValue))
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