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Don't assume that a left-shift of a value with one bit set will have
one bit set, because the bit may be shifted off the end. Instead, just check for a constant 1 being shifted. This is still sufficient to handle all the cases in test/CodeGen/X86/bt.ll. This fixes PR3583. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64622 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1346,14 +1346,31 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
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return 1;
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}
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/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
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/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
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/// determine which bit is set.
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///
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static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
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// Logical shift right or left won't ever introduce new set bits.
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// We check for this case because we don't care which bits are
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// set, but ComputeMaskedBits won't know anything unless it can
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// determine which specific bits may be set.
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if (Val.getOpcode() == ISD::SHL || Val.getOpcode() == ISD::SRL)
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return ValueHasExactlyOneBitSet(Val.getOperand(0), DAG);
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// A left-shift of a constant one will have exactly one bit set, because
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// shifting the bit off the end is undefined.
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if (Val.getOpcode() == ISD::SHL)
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
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if (C->getAPIntValue() == 1)
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return true;
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// Similarly, a right-shift of a constant sign-bit will have exactly
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// one bit set.
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if (Val.getOpcode() == ISD::SRL)
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
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if (C->getAPIntValue().isSignBit())
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return true;
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// More could be done here, though the above checks are enough
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// to handle some common cases.
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// Fall back to ComputeMaskedBits to catch other known cases.
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MVT OpVT = Val.getValueType();
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unsigned BitWidth = OpVT.getSizeInBits();
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APInt Mask = APInt::getAllOnesValue(BitWidth);
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