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InstCombine: Add a few missing combines for ANDs and ORs of sign bit tests.

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On x86 we now compile "if (a < 0 && b < 0)" into
	testl	%edi, %esi
	js	IF.THEN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-03-29 22:06:41 +00:00
parent b715ce35d7
commit 9822b869fc
2 changed files with 103 additions and 0 deletions
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24
lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
View File

@ -756,6 +756,18 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
Value *NewOr = Builder->CreateOr(Val, Val2);
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
}
// (icmp slt A, 0) & (icmp slt B, 0) --> (icmp slt (A&B), 0)
if (LHSCC == ICmpInst::ICMP_SLT && LHSCst->isZero()) {
Value *NewAnd = Builder->CreateAnd(Val, Val2);
return Builder->CreateICmp(LHSCC, NewAnd, LHSCst);
}
// (icmp sgt A, -1) & (icmp sgt B, -1) --> (icmp sgt (A|B), -1)
if (LHSCC == ICmpInst::ICMP_SGT && LHSCst->isAllOnesValue()) {
Value *NewOr = Builder->CreateOr(Val, Val2);
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
}
}
// From here on, we only handle:
@ -1442,6 +1454,18 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
Value *NewOr = Builder->CreateOr(Val, Val2);
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
}
// (icmp slt A, 0) | (icmp slt B, 0) --> (icmp slt (A|B), 0)
if (LHSCC == ICmpInst::ICMP_SLT && LHSCst->isZero()) {
Value *NewOr = Builder->CreateOr(Val, Val2);
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
}
// (icmp sgt A, -1) | (icmp sgt B, -1) --> (icmp sgt (A&B), -1)
if (LHSCC == ICmpInst::ICMP_SGT && LHSCst->isAllOnesValue()) {
Value *NewAnd = Builder->CreateAnd(Val, Val2);
return Builder->CreateICmp(LHSCC, NewAnd, LHSCst);
}
}
// (icmp ult (X + CA), C1) | (icmp eq X, C2) -> (icmp ule (X + CA), C1)

79
test/Transforms/InstCombine/sign-test-and-or.ll Normal file
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@ -0,0 +1,79 @@
; RUN: opt -S -instcombine < %s | FileCheck %s
declare void @foo()
define void @test1(i32 %a, i32 %b) nounwind {
%1 = icmp slt i32 %a, 0
%2 = icmp slt i32 %b, 0
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test1
; CHECK-NEXT: %1 = or i32 %a, %b
; CHECK-NEXT: %2 = icmp slt i32 %1, 0
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test2(i32 %a, i32 %b) nounwind {
%1 = icmp sgt i32 %a, -1
%2 = icmp sgt i32 %b, -1
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test2
; CHECK-NEXT: %1 = and i32 %a, %b
; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test3(i32 %a, i32 %b) nounwind {
%1 = icmp slt i32 %a, 0
%2 = icmp slt i32 %b, 0
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test3
; CHECK-NEXT: %1 = and i32 %a, %b
; CHECK-NEXT: %2 = icmp slt i32 %1, 0
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test4(i32 %a, i32 %b) nounwind {
%1 = icmp sgt i32 %a, -1
%2 = icmp sgt i32 %b, -1
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test4
; CHECK-NEXT: %1 = or i32 %a, %b
; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}