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Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
other targets. Use autogenerated calling conv to lower result of calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48444 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
5a65b92830
commit
98949a6d2c
@ -33,7 +33,7 @@ using namespace llvm;
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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// CCValAssign - represent the assignment of the return value to locations.
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SmallVector<CCValAssign, 16> RVLocs;
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
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// CCState - Info about the registers and stack slot.
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@ -235,15 +235,16 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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unsigned CC, bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG) {
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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SDOperand Chain = Op.getOperand(0);
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SDOperand Callee = Op.getOperand(4);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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// Count the size of the outgoing arguments.
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unsigned ArgsSize = 0;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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switch (getValueType(Args[i].Ty)) {
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for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
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switch (Op.getOperand(i).getValueType()) {
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default: assert(0 && "Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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@ -266,14 +267,14 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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// Keep stack frames 8-byte aligned.
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ArgsSize = (ArgsSize+7) & ~7;
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, MVT::i32));
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SDOperand StackPtr;
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std::vector<SDOperand> Stores;
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std::vector<SDOperand> RegValuesToPass;
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unsigned ArgOffset = 68;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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SDOperand Val = Args[i].Node;
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for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) {
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SDOperand Val = Op.getOperand(i);
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MVT::ValueType ObjectVT = Val.getValueType();
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SDOperand ValToStore(0, 0);
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unsigned ObjSize;
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@ -282,12 +283,13 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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case MVT::i1:
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case MVT::i8:
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case MVT::i16: {
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assert(0 && "unreach");
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// Promote the integer to 32-bits. If the input type is signed, use a
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// sign extend, otherwise use a zero extend.
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (Args[i].isSExt)
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if (Op.getConstantOperandVal(i+1) & 1)
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ExtendKind = ISD::SIGN_EXTEND;
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else if (Args[i].isZExt)
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else
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ExtendKind = ISD::ZERO_EXTEND;
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Val = DAG.getNode(ExtendKind, MVT::i32, Val);
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// FALL THROUGH
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@ -332,9 +334,9 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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}
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// Split the value into top and bottom part. Top part goes in a reg.
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
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SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
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DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
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DAG.getConstant(0, MVT::i32));
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RegValuesToPass.push_back(Hi);
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@ -352,7 +354,7 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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if (!StackPtr.Val) {
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StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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}
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
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}
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@ -390,59 +392,37 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
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InFlag = Chain.getValue(1);
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MVT::ValueType RetTyVT = getValueType(RetTy);
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(ArgsSize, MVT::i32),
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DAG.getConstant(0, MVT::i32), InFlag);
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InFlag = Chain.getValue(1);
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SDOperand RetVal;
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if (RetTyVT != MVT::isVoid) {
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switch (RetTyVT) {
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default: assert(0 && "Unknown value type to return!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16: {
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RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
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Chain = RetVal.getValue(1);
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// Add a note to keep track of whether it is sign or zero extended.
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ISD::NodeType AssertKind = ISD::DELETED_NODE;
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if (RetSExt)
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AssertKind = ISD::AssertSext;
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else if (RetZExt)
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AssertKind = ISD::AssertZext;
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if (AssertKind != ISD::DELETED_NODE)
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RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
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DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
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break;
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}
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case MVT::i32:
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RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::f32:
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RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::f64:
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RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::i64:
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SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
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SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
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Lo.getValue(2));
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RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
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Chain = Hi.getValue(1);
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break;
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}
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
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CCInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32);
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SmallVector<SDOperand, 8> ResultVals;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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unsigned Reg = RVLocs[i].getLocReg();
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// Remap I0->I7 -> O0->O7.
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if (Reg >= SP::I0 && Reg <= SP::I7)
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Reg = Reg-SP::I0+SP::O0;
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Chain = DAG.getCopyFromReg(Chain, Reg,
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RVLocs[i].getValVT(), InFlag).getValue(1);
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InFlag = Chain.getValue(2);
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ResultVals.push_back(Chain.getValue(0));
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}
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(ArgsSize, getPointerTy()),
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DAG.getConstant(0, getPointerTy()),
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SDOperand());
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return std::make_pair(RetVal, Chain);
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ResultVals.push_back(Chain);
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// Merge everything together with a MERGE_VALUES node.
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return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
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&ResultVals[0], ResultVals.size());
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}
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@ -866,6 +846,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
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case ISD::VAARG: return LowerVAARG(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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}
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}
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@ -59,11 +59,6 @@ namespace llvm {
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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unsigned CC, bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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