mirror of
https://github.com/RPCSX/llvm.git
synced 2024-11-24 20:29:53 +00:00
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
71280b55a3
commit
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@ -70,6 +70,7 @@ public:
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/// @param address - The address, in the memory space of region, of the first
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/// byte of the instruction.
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/// @param vStream - The stream to print warnings and diagnostic messages on.
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/// @param cStream - The stream to print comments and annotations on.
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/// @return - MCDisassembler::Success if the instruction is valid,
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/// MCDisassembler::SoftFail if the instruction was
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/// disassemblable but invalid,
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@ -78,7 +79,8 @@ public:
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uint64_t& size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const = 0;
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raw_ostream &vStream,
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raw_ostream &cStream) const = 0;
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/// getEDInfo - Returns the enhanced instruction information corresponding to
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/// the disassembler.
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@ -129,7 +129,6 @@ public:
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class MCInst {
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unsigned Opcode;
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SmallVector<MCOperand, 8> Operands;
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SmallVector<std::string, 1> Annotations;
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public:
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MCInst() : Opcode(0) {}
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@ -145,15 +144,7 @@ public:
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Operands.push_back(Op);
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}
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void addAnnotation(const std::string &Annot) {
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Annotations.push_back(Annot);
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}
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void clear() {
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Operands.clear();
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Annotations.clear();
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}
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void clear() { Operands.clear(); }
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size_t size() { return Operands.size(); }
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typedef SmallVector<MCOperand, 8>::iterator iterator;
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@ -163,9 +154,6 @@ public:
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return Operands.insert(I, Op);
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}
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size_t getNumAnnotations() const { return Annotations.size(); }
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std::string getAnnotation(size_t i) const { return Annotations[i]; }
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void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
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void dump() const;
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@ -28,6 +28,9 @@ protected:
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/// The current set of available features.
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unsigned AvailableFeatures;
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/// Utility function for printing annotations.
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void printAnnotation(raw_ostream &OS, StringRef Annot);
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public:
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MCInstPrinter(const MCAsmInfo &mai)
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: CommentStream(0), MAI(mai), AvailableFeatures(0) {}
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@ -39,11 +42,8 @@ public:
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/// printInst - Print the specified MCInst to the specified raw_ostream.
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///
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virtual void printInst(const MCInst *MI, raw_ostream &OS) = 0;
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/// printAnnotations - Print the annotation comments attached to specified
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/// MCInst to the specified raw_ostream.
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void printAnnotations(const MCInst *MI, raw_ostream &OS);
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virtual void printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annot) = 0;
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/// getOpcodeName - Return the name of the specified opcode enum (e.g.
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/// "MOV32ri") or empty if we can't resolve it.
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@ -1244,7 +1244,7 @@ void MCAsmStreamer::EmitInstruction(const MCInst &Inst) {
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// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
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if (InstPrinter)
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InstPrinter->printInst(&Inst, OS);
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InstPrinter->printInst(&Inst, OS, "");
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else
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Inst.print(OS, &MAI);
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EmitEOL();
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@ -144,7 +144,7 @@ size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
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MCInstPrinter *IP = DC->getIP();
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MCDisassembler::DecodeStatus S;
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S = DisAsm->getInstruction(Inst, Size, MemoryObject, PC,
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/*REMOVE*/ nulls());
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/*REMOVE*/ nulls(), DC->CommentStream);
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switch (S) {
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case MCDisassembler::Fail:
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case MCDisassembler::SoftFail:
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@ -152,28 +152,16 @@ size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
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return 0;
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case MCDisassembler::Success: {
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SmallVector<char, 64> InsnStr;
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raw_svector_ostream OS(InsnStr);
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IP->printInst(&Inst, OS);
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OS.flush();
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DC->CommentStream.flush();
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assert(DC->CommentsToEmit.back() == '\n');
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DC->CommentsToEmit.push_back('\n');
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StringRef Comments = DC->CommentsToEmit.str();
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do {
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// Emit a line of comments.
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size_t Position = Comments.find('\n');
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OS << ' ' << DC->getAsmInfo()->getCommentString()
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<< ' ' << Comments.substr(0, Position) << '\n';
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SmallVector<char, 64> InsnStr;
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raw_svector_ostream OS(InsnStr);
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IP->printInst(&Inst, OS, Comments);
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OS.flush();
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Comments = Comments.substr(Position+1);
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} while (!Comments.empty());
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DC->CommentsToEmit.clear();
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// Tell the comment stream that the vector changed underneath it.
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DC->CommentsToEmit.clear();
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DC->CommentStream.resync();
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assert(OutStringSize != 0 && "Output buffer cannot be zero size");
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@ -246,7 +246,7 @@ EDInst *EDDisassembler::createInst(EDByteReaderCallback byteReader,
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MCDisassembler::DecodeStatus S;
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S = Disassembler->getInstruction(*inst, byteSize, memoryObject, address,
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ErrorStream);
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ErrorStream, nulls());
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switch (S) {
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case MCDisassembler::Fail:
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case MCDisassembler::SoftFail:
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@ -327,7 +327,7 @@ bool EDDisassembler::registerIsProgramCounter(unsigned registerID) {
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int EDDisassembler::printInst(std::string &str, MCInst &inst) {
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PrinterMutex.acquire();
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InstPrinter->printInst(&inst, *InstStream);
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InstPrinter->printInst(&inst, *InstStream, "");
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InstStream->flush();
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str = *InstString;
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InstString->clear();
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@ -41,16 +41,6 @@ void MCInst::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
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OS << " ";
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getOperand(i).print(OS, MAI);
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}
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if (getNumAnnotations()) {
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OS << " # Annots: ";
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for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
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OS << " \"";
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OS << getAnnotation(i);
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OS << '"';
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}
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}
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OS << ">";
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}
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@ -67,17 +57,6 @@ void MCInst::dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI,
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OS << Separator;
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getOperand(i).print(OS, MAI);
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}
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if (getNumAnnotations()) {
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OS << " # Annots: ";
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for (unsigned i = 0, e = getNumAnnotations(); i != e; ++i) {
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OS << Separator;
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OS << '"';
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OS << getAnnotation(i);
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OS << '"';
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}
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}
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OS << ">";
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}
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@ -8,8 +8,6 @@
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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@ -27,8 +25,6 @@ void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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assert(0 && "Target should implement this");
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}
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void MCInstPrinter::printAnnotations(const MCInst *MI, raw_ostream &OS) {
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for (unsigned i = 0, e = MI->getNumAnnotations(); i != e; ++i) {
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OS << MI->getAnnotation(i) << "\n";
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}
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void MCInstPrinter::printAnnotation(raw_ostream &OS, StringRef Annot) {
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if (!Annot.empty()) OS << Annot << "\n";
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}
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@ -47,7 +47,8 @@ public:
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const;
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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/// getEDInfo - See MCDisassembler.
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EDInstInfo *getEDInfo() const;
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@ -71,7 +72,8 @@ public:
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const;
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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/// getEDInfo - See MCDisassembler.
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EDInstInfo *getEDInfo() const;
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@ -328,7 +330,8 @@ EDInstInfo *ThumbDisassembler::getEDInfo() const {
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DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os) const {
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raw_ostream &os,
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raw_ostream &cs) const {
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uint8_t bytes[4];
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assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
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@ -527,7 +530,8 @@ void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
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DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os) const {
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raw_ostream &os,
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raw_ostream &cs) const {
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uint8_t bytes[4];
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assert((STI.getFeatureBits() & ARM::ModeThumb) &&
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@ -51,7 +51,8 @@ void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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unsigned Opcode = MI->getOpcode();
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// Check for MOVs and print canonical forms, instead.
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@ -71,9 +72,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ", " << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -91,13 +90,12 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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<< ", " << getRegisterName(MO1.getReg());
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if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -111,7 +109,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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@ -119,7 +117,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << '\t' << "push";
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printPredicateOperand(MI, 4, O);
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O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -132,7 +130,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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@ -140,7 +138,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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O << '\t' << "pop";
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printPredicateOperand(MI, 5, O);
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O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -152,7 +150,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -163,7 +161,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -182,7 +180,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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if (Writeback) O << "!";
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O << ", ";
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printRegisterList(MI, 3, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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@ -191,12 +189,12 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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MI->getOperand(1).getReg() == ARM::R8) {
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O << "\tnop";
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printPredicateOperand(MI, 2, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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return;
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}
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printInstruction(MI, O);
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if (CommentStream) printAnnotations(MI, *CommentStream);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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@ -25,7 +25,7 @@ class ARMInstPrinter : public MCInstPrinter {
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public:
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ARMInstPrinter(const MCAsmInfo &MAI, const MCSubtargetInfo &STI);
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virtual void printInst(const MCInst *MI, raw_ostream &O);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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@ -497,7 +497,8 @@ MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const {
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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// The machine instruction.
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uint32_t insn;
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uint64_t read;
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@ -44,7 +44,8 @@ public:
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const;
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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/// getEDInfo - See MCDisassembler.
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EDInstInfo *getEDInfo() const;
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@ -25,8 +25,10 @@ using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#include "MBlazeGenAsmWriter.inc"
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void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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printInstruction(MI, O);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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}
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void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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@ -24,7 +24,7 @@ namespace llvm {
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MBlazeInstPrinter(const MCAsmInfo &MAI)
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: MCInstPrinter(MAI) {}
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virtual void printInst(const MCInst *MI, raw_ostream &O);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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@ -25,8 +25,10 @@ using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#include "MSP430GenAsmWriter.inc"
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void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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printInstruction(MI, O);
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if (CommentStream) printAnnotation(*CommentStream, Annot);
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}
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void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
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@ -24,7 +24,7 @@ namespace llvm {
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MSP430InstPrinter(const MCAsmInfo &MAI)
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: MCInstPrinter(MAI) {}
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virtual void printInst(const MCInst *MI, raw_ostream &O);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
|
||||
|
@ -69,8 +69,10 @@ void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
|
||||
OS << '$' << LowercaseString(getRegisterName(RegNo));
|
||||
}
|
||||
|
||||
void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
|
||||
void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
|
||||
StringRef Annot) {
|
||||
printInstruction(MI, O);
|
||||
if (CommentStream) printAnnotation(*CommentStream, Annot);
|
||||
}
|
||||
|
||||
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||||
|
@ -86,7 +86,7 @@ public:
|
||||
|
||||
virtual StringRef getOpcodeName(unsigned Opcode) const;
|
||||
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O);
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
|
||||
|
||||
private:
|
||||
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
|
@ -513,7 +513,7 @@ void PTXMCAsmStreamer::EmitInstruction(const MCInst &Inst) {
|
||||
|
||||
// If we have an AsmPrinter, use that to print, otherwise print the MCInst.
|
||||
if (InstPrinter)
|
||||
InstPrinter->printInst(&Inst, OS);
|
||||
InstPrinter->printInst(&Inst, OS, "");
|
||||
else
|
||||
Inst.print(OS, &MAI);
|
||||
EmitEOL();
|
||||
|
@ -31,7 +31,8 @@ void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
|
||||
OS << getRegisterName(RegNo);
|
||||
}
|
||||
|
||||
void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
|
||||
void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
|
||||
StringRef Annot) {
|
||||
// Check for slwi/srwi mnemonics.
|
||||
if (MI->getOpcode() == PPC::RLWINM) {
|
||||
unsigned char SH = MI->getOperand(2).getImm();
|
||||
@ -50,6 +51,8 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
O << ", " << (unsigned int)SH;
|
||||
|
||||
if (CommentStream) printAnnotation(*CommentStream, Annot);
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -60,6 +63,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
|
||||
printOperand(MI, 0, O);
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
if (CommentStream) printAnnotation(*CommentStream, Annot);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -73,11 +77,13 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
O << ", " << (unsigned int)SH;
|
||||
if (CommentStream) printAnnotation(*CommentStream, Annot);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
printInstruction(MI, O);
|
||||
if (CommentStream) printAnnotation(*CommentStream, Annot);
|
||||
}
|
||||
|
||||
|
||||
|
@ -32,7 +32,7 @@ public:
|
||||
}
|
||||
|
||||
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O);
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
|
||||
virtual StringRef getOpcodeName(unsigned Opcode) const;
|
||||
|
||||
static const char *getInstructionName(unsigned Opcode);
|
||||
|
@ -114,7 +114,8 @@ X86GenericDisassembler::getInstruction(MCInst &instr,
|
||||
uint64_t &size,
|
||||
const MemoryObject ®ion,
|
||||
uint64_t address,
|
||||
raw_ostream &vStream) const {
|
||||
raw_ostream &vStream,
|
||||
raw_ostream &cStream) const {
|
||||
InternalInstruction internalInstr;
|
||||
|
||||
int ret = decodeInstruction(&internalInstr,
|
||||
|
@ -117,7 +117,8 @@ public:
|
||||
uint64_t &size,
|
||||
const MemoryObject ®ion,
|
||||
uint64_t address,
|
||||
raw_ostream &vStream) const;
|
||||
raw_ostream &vStream,
|
||||
raw_ostream &cStream) const;
|
||||
|
||||
/// getEDInfo - See MCDisassembler.
|
||||
EDInstInfo *getEDInfo() const;
|
||||
|
@ -39,14 +39,15 @@ void X86ATTInstPrinter::printRegName(raw_ostream &OS,
|
||||
OS << '%' << getRegisterName(RegNo);
|
||||
}
|
||||
|
||||
void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
|
||||
void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
StringRef Annot) {
|
||||
// Try to print any aliases first.
|
||||
if (!printAliasInstr(MI, OS))
|
||||
printInstruction(MI, OS);
|
||||
|
||||
// If verbose assembly is enabled, we can print some informative comments.
|
||||
if (CommentStream) {
|
||||
printAnnotations(MI, *CommentStream);
|
||||
printAnnotation(*CommentStream, Annot);
|
||||
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
|
||||
}
|
||||
}
|
||||
|
@ -25,7 +25,7 @@ public:
|
||||
X86ATTInstPrinter(const MCAsmInfo &MAI);
|
||||
|
||||
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &OS);
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
|
||||
virtual StringRef getOpcodeName(unsigned Opcode) const;
|
||||
|
||||
// Autogenerated by tblgen, returns true if we successfully printed an
|
||||
|
@ -32,12 +32,13 @@ void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
|
||||
OS << getRegisterName(RegNo);
|
||||
}
|
||||
|
||||
void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
|
||||
void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
StringRef Annot) {
|
||||
printInstruction(MI, OS);
|
||||
|
||||
// If verbose assembly is enabled, we can print some informative comments.
|
||||
if (CommentStream) {
|
||||
printAnnotations(MI, *CommentStream);
|
||||
printAnnotation(*CommentStream, Annot);
|
||||
EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
|
||||
}
|
||||
}
|
||||
|
@ -27,7 +27,7 @@ public:
|
||||
: MCInstPrinter(MAI) {}
|
||||
|
||||
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &OS);
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
|
||||
virtual StringRef getOpcodeName(unsigned Opcode) const;
|
||||
|
||||
// Autogenerated by tblgen.
|
||||
|
@ -68,7 +68,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm,
|
||||
|
||||
MCDisassembler::DecodeStatus S;
|
||||
S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
|
||||
/*REMOVE*/ nulls());
|
||||
/*REMOVE*/ nulls(), nulls());
|
||||
switch (S) {
|
||||
case MCDisassembler::Fail:
|
||||
SM.PrintMessage(SMLoc::getFromPointer(Bytes[Index].second),
|
||||
@ -83,7 +83,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm,
|
||||
// Fall through
|
||||
|
||||
case MCDisassembler::Success:
|
||||
Printer.printInst(&Inst, Out);
|
||||
Printer.printInst(&Inst, Out, "");
|
||||
Out << "\n";
|
||||
break;
|
||||
}
|
||||
|
@ -40,7 +40,7 @@ MCFunction::createFunctionFromMC(StringRef Name, const MCDisassembler *DisAsm,
|
||||
for (uint64_t Index = Start; Index < End; Index += Size) {
|
||||
MCInst Inst;
|
||||
|
||||
if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut)) {
|
||||
if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())) {
|
||||
if (Ana->isBranch(Inst)) {
|
||||
uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
|
||||
// FIXME: Distinguish relocations from nop jumps.
|
||||
|
@ -262,13 +262,14 @@ static void DisassembleInput(const StringRef &Filename) {
|
||||
if (!CFG) {
|
||||
for (Index = Start; Index < End; Index += Size) {
|
||||
MCInst Inst;
|
||||
|
||||
if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
|
||||
DebugOut)) {
|
||||
DebugOut, nulls())) {
|
||||
uint64_t addr;
|
||||
if (error(i->getAddress(addr))) break;
|
||||
outs() << format("%8x:\t", addr + Index);
|
||||
DumpBytes(StringRef(Bytes.data() + Index, Size));
|
||||
IP->printInst(&Inst, outs());
|
||||
IP->printInst(&Inst, outs(), "");
|
||||
outs() << "\n";
|
||||
} else {
|
||||
errs() << ToolName << ": warning: invalid instruction encoding\n";
|
||||
@ -323,7 +324,7 @@ static void DisassembleInput(const StringRef &Filename) {
|
||||
// Simple loops.
|
||||
if (fi->second.contains(&fi->second))
|
||||
outs() << '\t';
|
||||
IP->printInst(&Inst.Inst, outs());
|
||||
IP->printInst(&Inst.Inst, outs(), "");
|
||||
outs() << '\n';
|
||||
}
|
||||
}
|
||||
@ -359,7 +360,7 @@ static void DisassembleInput(const StringRef &Filename) {
|
||||
// Escape special chars and print the instruction in mnemonic form.
|
||||
std::string Str;
|
||||
raw_string_ostream OS(Str);
|
||||
IP->printInst(&i->second.getInsts()[ii].Inst, OS);
|
||||
IP->printInst(&i->second.getInsts()[ii].Inst, OS, "");
|
||||
Out << DOT::EscapeString(OS.str()) << '|';
|
||||
}
|
||||
Out << "<o>\" shape=\"record\" ];\n";
|
||||
|
Loading…
Reference in New Issue
Block a user