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Allow large immediates for branch instructions in 32bit mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215240 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger 2014-08-08 20:57:58 +00:00
parent f0b70e2fbc
commit 996a304351
2 changed files with 23 additions and 3 deletions
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20
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -432,9 +432,23 @@ public:
bool isS17Imm() const { return Kind == Expression ||
(Kind == Immediate && isInt<17>(getImm())); }
bool isTLSReg() const { return Kind == TLSRegister; }
bool isDirectBr() const { return Kind == Expression ||
(Kind == Immediate && isInt<26>(getImm()) &&
(getImm() & 3) == 0); }
bool isDirectBr() const {
if (Kind == Expression)
return true;
if (Kind != Immediate)
return false;
// Operand must be 64-bit aligned, signed 27-bit immediate.
if ((getImm() & 3) != 0)
return false;
if (isInt<26>(getImm()))
return true;
if (!IsPPC64) {
// In 32-bit mode, large 32-bit quantities wrap around.
if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
return true;
}
return false;
}
bool isCondBr() const { return Kind == Expression ||
(Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 3) == 0); }

6
test/MC/PowerPC/ppc32-ba.s Normal file
View File

@ -0,0 +1,6 @@
# RUN: llvm-mc -triple powerpc-unknown-unknown --show-encoding %s | FileCheck %s
# Check that large immediates in 32bit mode are accepted.
# CHECK: ba -33554432 # encoding: [0x4a,0x00,0x00,0x02]
ba 0xfe000000