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[Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
cb2753f32e
commit
99719f40ee
@ -94,11 +94,6 @@ public:
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void SelectLoad(SDNode *N);
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void SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
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void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
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void SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
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const SDLoc &dl);
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void SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
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const SDLoc &dl);
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void SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
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void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
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void SelectStore(SDNode *N);
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void SelectSHL(SDNode *N);
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@ -241,128 +236,11 @@ static bool doesIntrinsicReturnPredicate(unsigned ID) {
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}
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}
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void HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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unsigned Opcode,
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const SDLoc &dl) {
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SDValue Chain = LD->getChain();
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EVT LoadedVT = LD->getMemoryVT();
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SDValue Base = LD->getBasePtr();
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SDValue Offset = LD->getOffset();
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SDNode *OffsetNode = Offset.getNode();
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int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
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if (HII->isValidAutoIncImm(LoadedVT, Val)) {
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SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
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MVT::Other, Base, TargetConst,
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Chain);
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
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SDValue(Result_1, 0));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2) };
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const SDValue Tos[] = { SDValue(Result_2, 0),
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SDValue(Result_1, 1),
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SDValue(Result_1, 2) };
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ReplaceUses(Froms, Tos, 3);
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
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Base, TargetConst0, Chain);
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
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SDValue(Result_1, 0));
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SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
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Base, TargetConstVal,
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SDValue(Result_1, 1));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2) };
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const SDValue Tos[] = { SDValue(Result_2, 0),
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SDValue(Result_3, 0),
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SDValue(Result_1, 1) };
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ReplaceUses(Froms, Tos, 3);
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CurDAG->RemoveDeadNode(LD);
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}
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void HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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unsigned Opcode,
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const SDLoc &dl) {
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SDValue Chain = LD->getChain();
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EVT LoadedVT = LD->getMemoryVT();
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SDValue Base = LD->getBasePtr();
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SDValue Offset = LD->getOffset();
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SDNode *OffsetNode = Offset.getNode();
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int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
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if (HII->isValidAutoIncImm(LoadedVT, Val)) {
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
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MVT::i32, MVT::Other, Base,
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TargetConstVal, Chain);
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
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MVT::i64, MVT::Other,
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TargetConst0,
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SDValue(Result_1,0));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2) };
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const SDValue Tos[] = { SDValue(Result_2, 0),
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SDValue(Result_1, 1),
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SDValue(Result_1, 2) };
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ReplaceUses(Froms, Tos, 3);
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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// Generate an indirect load.
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
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MVT::Other, Base, TargetConst0,
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Chain);
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
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MVT::i64, MVT::Other,
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TargetConst0,
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SDValue(Result_1,0));
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// Add offset to base.
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SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
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Base, TargetConstVal,
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SDValue(Result_1, 1));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2) };
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const SDValue Tos[] = { SDValue(Result_2, 0), // Load value.
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SDValue(Result_3, 0), // New address.
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SDValue(Result_1, 1) };
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ReplaceUses(Froms, Tos, 3);
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
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SDValue Chain = LD->getChain();
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SDValue Base = LD->getBasePtr();
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SDValue Offset = LD->getOffset();
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SDNode *OffsetNode = Offset.getNode();
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// Get the constant value.
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int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
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int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
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EVT LoadedVT = LD->getMemoryVT();
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unsigned Opcode = 0;
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@ -370,119 +248,110 @@ void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
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// loads.
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ISD::LoadExtType ExtType = LD->getExtensionType();
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bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
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bool HasVecOffset = false;
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bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc);
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// Figure out the opcode.
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if (LoadedVT == MVT::i64) {
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::L2_loadrd_pi;
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assert(LoadedVT.isSimple());
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switch (LoadedVT.getSimpleVT().SimpleTy) {
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case MVT::i8:
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if (IsZeroExt)
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Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
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else
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Opcode = Hexagon::L2_loadrd_io;
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} else if (LoadedVT == MVT::i32) {
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::L2_loadri_pi;
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Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
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break;
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case MVT::i16:
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if (IsZeroExt)
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Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
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else
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Opcode = Hexagon::L2_loadri_io;
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} else if (LoadedVT == MVT::i16) {
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
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Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
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break;
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case MVT::i32:
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Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
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break;
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case MVT::i64:
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Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
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break;
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// 64B
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case MVT::v64i8:
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case MVT::v32i16:
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case MVT::v16i32:
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case MVT::v8i64:
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if (isAlignedMemNode(LD))
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Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
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else
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Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
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} else if (LoadedVT == MVT::i8) {
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
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else
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Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
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} else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 ||
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LoadedVT == MVT::v32i16 || LoadedVT == MVT::v64i8) {
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HasVecOffset = true;
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bool Aligned = isAlignedMemNode(LD);
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Aligned ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32Ub_pi;
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else
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Opcode = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
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Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
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break;
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// 128B
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} else if (LoadedVT == MVT::v32i32 || LoadedVT == MVT::v16i64 ||
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LoadedVT == MVT::v64i16 || LoadedVT == MVT::v128i8) {
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if (HST->useHVXOps()) {
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bool Aligned = isAlignedMemNode(LD);
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HasVecOffset = true;
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if (HII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Aligned ? Hexagon::V6_vL32b_pi_128B
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: Hexagon::V6_vL32Ub_pi_128B;
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case MVT::v128i8:
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case MVT::v64i16:
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case MVT::v32i32:
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case MVT::v16i64:
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if (isAlignedMemNode(LD))
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Opcode = IsValidInc ? Hexagon::V6_vL32b_pi_128B
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: Hexagon::V6_vL32b_ai_128B;
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else
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Opcode = Aligned ? Hexagon::V6_vL32b_ai_128B
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Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi_128B
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: Hexagon::V6_vL32Ub_ai_128B;
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}
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} else
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llvm_unreachable("unknown memory type");
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// For zero extended i64 loads, we need to add combine instructions.
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if (LD->getValueType(0) == MVT::i64 && IsZeroExt) {
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SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
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return;
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}
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// Handle sign extended i64 loads.
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if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD) {
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SelectIndexedLoadSignExtend64(LD, Opcode, dl);
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return;
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break;
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default:
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llvm_unreachable("Unexpected memory type in indexed load");
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}
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if (HII->isValidAutoIncImm(LoadedVT, Val)) {
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
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LD->getValueType(0),
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SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
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-> MachineSDNode* {
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if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
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SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
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return CurDAG->getMachineNode(Hexagon::A4_combineir, dl, MVT::i64,
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Zero, SDValue(N, 0));
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}
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if (ExtType == ISD::SEXTLOAD)
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return CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
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SDValue(N, 0));
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return N;
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};
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// Loaded value Next address Chain
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SDValue From[3] = { SDValue(LD,0), SDValue(LD,1), SDValue(LD,2) };
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SDValue To[3];
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EVT ValueVT = LD->getValueType(0);
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if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
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// A load extending to i64 will actually produce i32, which will then
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// need to be extended to i64.
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assert(LoadedVT.getSizeInBits() <= 32);
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ValueVT = MVT::i32;
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}
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if (IsValidInc) {
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MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT,
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MVT::i32, MVT::Other, Base,
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TargetConstVal, Chain);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
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if (HasVecOffset) {
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 2)
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};
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const SDValue Tos[] = { SDValue(Result, 0),
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SDValue(Result, 2)
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};
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ReplaceUses(Froms, Tos, 2);
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IncV, Chain);
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L->setMemRefs(MemOp, MemOp+1);
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To[1] = SDValue(L, 1); // Next address.
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To[2] = SDValue(L, 2); // Chain.
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// Handle special case for extension to i64.
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if (LD->getValueType(0) == MVT::i64)
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L = getExt64(L, dl);
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To[0] = SDValue(L, 0); // Loaded (extended) value.
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} else {
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2)
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};
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const SDValue Tos[] = { SDValue(Result, 0),
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SDValue(Result, 1),
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SDValue(Result, 2)
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};
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ReplaceUses(Froms, Tos, 3);
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SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
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MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other,
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Base, Zero, Chain);
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L->setMemRefs(MemOp, MemOp+1);
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To[2] = SDValue(L, 1); // Chain.
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MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
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Base, IncV);
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To[1] = SDValue(A, 0); // Next address.
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// Handle special case for extension to i64.
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if (LD->getValueType(0) == MVT::i64)
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L = getExt64(L, dl);
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To[0] = SDValue(L, 0); // Loaded (extended) value.
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}
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ReplaceUses(From, To, 3);
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CurDAG->RemoveDeadNode(LD);
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return;
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} else {
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
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LD->getValueType(0),
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MVT::Other, Base, TargetConst0,
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Chain);
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SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
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Base, TargetConstVal,
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SDValue(Result_1, 1));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2)
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};
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const SDValue Tos[] = { SDValue(Result_1, 0),
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SDValue(Result_2, 0),
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SDValue(Result_1, 1)
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};
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ReplaceUses(Froms, Tos, 3);
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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}
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@ -644,7 +513,6 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
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return false;
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}
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void HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
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SDLoc dl(N);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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@ -668,104 +536,89 @@ void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
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SDValue Base = ST->getBasePtr();
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SDValue Offset = ST->getOffset();
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SDValue Value = ST->getValue();
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SDNode *OffsetNode = Offset.getNode();
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// Get the constant value.
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int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
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int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
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EVT StoredVT = ST->getMemoryVT();
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EVT ValueVT = Value.getValueType();
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// Offset value must be within representable range
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// and must have correct alignment properties.
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if (HII->isValidAutoIncImm(StoredVT, Val)) {
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bool IsValidInc = HII->isValidAutoIncImm(StoredVT, Inc);
|
||||
unsigned Opcode = 0;
|
||||
|
||||
// Figure out the post inc version of opcode.
|
||||
if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
|
||||
else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
|
||||
else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
|
||||
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
|
||||
else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
|
||||
StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) {
|
||||
assert(StoredVT.isSimple());
|
||||
switch (StoredVT.getSimpleVT().SimpleTy) {
|
||||
case MVT::i8:
|
||||
Opcode = IsValidInc ? Hexagon::S2_storerb_pi : Hexagon::S2_storerb_io;
|
||||
break;
|
||||
case MVT::i16:
|
||||
Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
|
||||
break;
|
||||
case MVT::i32:
|
||||
Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
|
||||
break;
|
||||
case MVT::i64:
|
||||
Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
|
||||
break;
|
||||
// 64B
|
||||
case MVT::v64i8:
|
||||
case MVT::v32i16:
|
||||
case MVT::v16i32:
|
||||
case MVT::v8i64:
|
||||
if (isAlignedMemNode(ST))
|
||||
Opcode = Hexagon::V6_vS32b_pi;
|
||||
Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
|
||||
else
|
||||
Opcode = Hexagon::V6_vS32Ub_pi;
|
||||
}
|
||||
Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
|
||||
break;
|
||||
// 128B
|
||||
else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
|
||||
StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) {
|
||||
if (HST->useHVXOps())
|
||||
Opcode = isAlignedMemNode(ST) ? Hexagon::V6_vS32b_pi_128B
|
||||
: Hexagon::V6_vS32Ub_pi_128B;
|
||||
} else
|
||||
llvm_unreachable("unknown memory type");
|
||||
case MVT::v128i8:
|
||||
case MVT::v64i16:
|
||||
case MVT::v32i32:
|
||||
case MVT::v16i64:
|
||||
if (isAlignedMemNode(ST))
|
||||
Opcode = IsValidInc ? Hexagon::V6_vS32b_pi_128B
|
||||
: Hexagon::V6_vS32b_ai_128B;
|
||||
else
|
||||
Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi_128B
|
||||
: Hexagon::V6_vS32Ub_ai_128B;
|
||||
break;
|
||||
default:
|
||||
llvm_unreachable("Unexpected memory type in indexed store");
|
||||
}
|
||||
|
||||
if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
|
||||
assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
|
||||
Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
|
||||
dl, MVT::i32, Value);
|
||||
}
|
||||
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
|
||||
Chain};
|
||||
|
||||
SDValue IncV = CurDAG->getTargetConstant(Inc, dl, MVT::i32);
|
||||
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
||||
MemOp[0] = ST->getMemOperand();
|
||||
|
||||
// Next address Chain
|
||||
SDValue From[2] = { SDValue(ST,0), SDValue(ST,1) };
|
||||
SDValue To[2];
|
||||
|
||||
if (IsValidInc) {
|
||||
// Build post increment store.
|
||||
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
|
||||
MVT::Other, Ops);
|
||||
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
||||
MemOp[0] = ST->getMemOperand();
|
||||
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
|
||||
SDValue Ops[] = { Base, IncV, Value, Chain };
|
||||
MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
|
||||
Ops);
|
||||
S->setMemRefs(MemOp, MemOp + 1);
|
||||
To[0] = SDValue(S, 0);
|
||||
To[1] = SDValue(S, 1);
|
||||
} else {
|
||||
SDValue Zero = CurDAG->getTargetConstant(0, dl, MVT::i32);
|
||||
SDValue Ops[] = { Base, Zero, Value, Chain };
|
||||
MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
|
||||
S->setMemRefs(MemOp, MemOp + 1);
|
||||
To[1] = SDValue(S, 0);
|
||||
MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
|
||||
Base, IncV);
|
||||
To[0] = SDValue(A, 0);
|
||||
}
|
||||
|
||||
ReplaceUses(ST, Result);
|
||||
ReplaceUses(SDValue(ST,1), SDValue(Result,1));
|
||||
ReplaceUses(From, To, 2);
|
||||
CurDAG->RemoveDeadNode(ST);
|
||||
return;
|
||||
}
|
||||
|
||||
// Note: Order of operands matches the def of instruction:
|
||||
// def S2_storerd_io
|
||||
// : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
|
||||
// and it differs for POST_ST* for instance.
|
||||
SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
|
||||
Chain};
|
||||
unsigned Opcode = 0;
|
||||
|
||||
// Figure out the opcode.
|
||||
if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
|
||||
else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
|
||||
else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
|
||||
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
|
||||
else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
|
||||
StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) {
|
||||
if (isAlignedMemNode(ST))
|
||||
Opcode = Hexagon::V6_vS32b_ai;
|
||||
else
|
||||
Opcode = Hexagon::V6_vS32Ub_ai;
|
||||
}
|
||||
// 128B
|
||||
else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
|
||||
StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) {
|
||||
if (isAlignedMemNode(ST))
|
||||
Opcode = Hexagon::V6_vS32b_ai_128B;
|
||||
else
|
||||
Opcode = Hexagon::V6_vS32Ub_ai_128B;
|
||||
}
|
||||
else llvm_unreachable("unknown memory type");
|
||||
|
||||
// Build regular store.
|
||||
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
|
||||
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
|
||||
// Build splitted incriment instruction.
|
||||
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
|
||||
Base,
|
||||
TargetConstVal,
|
||||
SDValue(Result_1, 0));
|
||||
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
||||
MemOp[0] = ST->getMemOperand();
|
||||
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
||||
|
||||
ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
|
||||
ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
|
||||
CurDAG->RemoveDeadNode(ST);
|
||||
return;
|
||||
}
|
||||
|
||||
void HexagonDAGToDAGISel::SelectStore(SDNode *N) {
|
||||
|
||||
52
test/CodeGen/Hexagon/vload-postinc-sel.ll
Normal file
52
test/CodeGen/Hexagon/vload-postinc-sel.ll
Normal file
@ -0,0 +1,52 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
; CHECK: = vmem(r{{[0-9]+}}++#1)
|
||||
|
||||
target triple = "hexagon-unknown--elf"
|
||||
|
||||
declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
|
||||
declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0
|
||||
declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0
|
||||
declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0
|
||||
declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
|
||||
declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
|
||||
declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0
|
||||
|
||||
define void @fred() #1 {
|
||||
entry:
|
||||
br i1 undef, label %b1, label %call_destructor.exit
|
||||
|
||||
b1: ; preds = %entry
|
||||
br label %b2
|
||||
|
||||
b2: ; preds = %b1, %b2
|
||||
%c2.host32.sroa.3.0 = phi <128 x i8> [ %5, %b2 ], [ undef, %b1 ]
|
||||
%sobel_halide.s0.x.x = phi i32 [ %17, %b2 ], [ 0, %b1 ]
|
||||
%0 = add nsw i32 %sobel_halide.s0.x.x, undef
|
||||
%1 = shl i32 %0, 7
|
||||
%2 = add nsw i32 %1, 128
|
||||
%3 = getelementptr inbounds i8, i8* undef, i32 %2
|
||||
%4 = bitcast i8* %3 to <128 x i8>*
|
||||
%5 = load <128 x i8>, <128 x i8>* %4, align 128
|
||||
%6 = bitcast <128 x i8> %c2.host32.sroa.3.0 to <32 x i32>
|
||||
%7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1)
|
||||
%8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1
|
||||
%9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1
|
||||
%10 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %9, <64 x i32> undef) #1
|
||||
%11 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %10)
|
||||
%12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %11) #1
|
||||
%13 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %12, <32 x i32> undef)
|
||||
%14 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %13) #1
|
||||
%15 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %14) #1
|
||||
%16 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %15, <32 x i32> undef) #1
|
||||
store <32 x i32> %16, <32 x i32>* undef, align 128
|
||||
%17 = add nuw nsw i32 %sobel_halide.s0.x.x, 1
|
||||
br label %b2
|
||||
|
||||
call_destructor.exit: ; preds = %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
|
||||
Loading…
x
Reference in New Issue
Block a user