RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-07 21:20:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Basic FP->Int, Int->FP conversions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-09-09 18:54:59 +00:00
parent ae4f7421c0
commit 9a040492f7
1 changed files with 55 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
lib/Target/ARM/ARMFastISel.cpp
View File

@ -116,6 +116,8 @@ class ARMFastISel : public FastISel {
virtual bool ARMSelectCmp(const Instruction *I);
virtual bool ARMSelectFPExt(const Instruction *I);
virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
virtual bool ARMSelectSIToFP(const Instruction *I);
virtual bool ARMSelectFPToSI(const Instruction *I);
// Utility routines.
private:
@ -741,6 +743,55 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
return true;
}
bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
// Make sure we have VFP.
if (!Subtarget->hasVFP2()) return false;
EVT VT;
const Type *Ty = I->getType();
if (!isTypeLegal(Ty, VT))
return false;
unsigned Op = getRegForValue(I->getOperand(0));
if (Op == 0) return false;
unsigned Opc;
if (Ty->isFloatTy()) Opc = ARM::VSITOS;
else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
else return 0;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg)
.addReg(Op));
return true;
}
bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
// Make sure we have VFP.
if (!Subtarget->hasVFP2()) return false;
EVT VT;
const Type *RetTy = I->getType();
if (!isTypeLegal(RetTy, VT))
return false;
unsigned Op = getRegForValue(I->getOperand(0));
if (Op == 0) return false;
unsigned Opc;
const Type *OpTy = I->getOperand(0)->getType();
if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
else return 0;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
ResultReg)
.addReg(Op));
return true;
}
bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
EVT VT = TLI.getValueType(I->getType(), true);
@ -798,6 +849,10 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
return ARMSelectCmp(I);
case Instruction::FPExt:
return ARMSelectFPExt(I);
case Instruction::SIToFP:
return ARMSelectSIToFP(I);
case Instruction::FPToSI:
return ARMSelectFPToSI(I);
case Instruction::FAdd:
return ARMSelectBinaryOp(I, ISD::FADD);
case Instruction::FSub: