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Add missing register constraint for some VLD3/VLD4 pseudo instructions.

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<rdar://problem/9878189>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-08-05 07:24:09 +00:00
parent 8d8fa2506d
commit 9a45008e91
1 changed files with 2 additions and 1 deletions
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3
lib/Target/ARM/ARMInstrNEON.td
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@ -175,7 +175,8 @@ class VLDQQWBPseudo<InstrItinClass itin>
(ins addrmode6:$addr, am6offset:$offset), itin,
"$addr.addr = $wb">;
class VLDQQQQPseudo<InstrItinClass itin>
: PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,"">;
: PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
"$src = $dst">;
class VLDQQQQWBPseudo<InstrItinClass itin>
: PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,