mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-12 14:17:59 +00:00
Simplify condition checking as CONCAT assume all inputs of the same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166260 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
89e7b356f2
commit
9aecdb51c7
@ -8629,9 +8629,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
|
|||||||
// (extract_subvec (concat V1, V2, ...), i)
|
// (extract_subvec (concat V1, V2, ...), i)
|
||||||
// Into:
|
// Into:
|
||||||
// Vi if possible
|
// Vi if possible
|
||||||
for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
|
// Only operand 0 is checked as 'concat' assumes all inputs of the same type.
|
||||||
if (V->getOperand(i).getValueType() != NVT)
|
if (V->getOperand(0).getValueType() != NVT)
|
||||||
return SDValue();
|
return SDValue();
|
||||||
unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
|
unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
|
||||||
unsigned NumElems = NVT.getVectorNumElements();
|
unsigned NumElems = NVT.getVectorNumElements();
|
||||||
assert((Idx % NumElems) == 0 &&
|
assert((Idx % NumElems) == 0 &&
|
||||||
|
Loading…
Reference in New Issue
Block a user