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[X86] Add target combine rules for horizontal add/sub.
This patch adds new target specific combine rules to identify horizontal
add/sub idioms from BUILD_VECTOR dag nodes.
This patch also teaches the DAGCombiner how to canonicalize sequences of
insert_vector_elt dag nodes according to the following rule:
(insert_vector_elt (insert_vector_elt A, I0), I1) ->
(insert_vecto_elt (insert_vector_elt A, I1), I0)
This new canonicalization rule only triggers if the inner insert_vector
dag node has exactly one use; also, both indices must be known constants,
and I1 < I0.
This last rule made it possible to write a simpler algorithm to identify
horizontal add/sub patterns because now we don't have to worry about the
ordering of insert_vector_elt dag nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210477 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
1968da36ed
commit
9b6992ddc2
@ -9721,6 +9721,27 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
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return SDValue();
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unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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// Canonicalize insert_vector_elt dag nodes.
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// Example:
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// (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
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// -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
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//
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// Do this only if the child insert_vector node has one use; also
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// do this only if indices are both constants and Idx1 < Idx0.
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if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
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&& isa<ConstantSDNode>(InVec.getOperand(2))) {
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unsigned OtherElt =
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cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
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if (Elt < OtherElt) {
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// Swap nodes.
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SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
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InVec.getOperand(0), InVal, EltNo);
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AddToWorkList(NewOp.getNode());
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
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VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
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}
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}
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// Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
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// be converted to a BUILD_VECTOR). Fill in the Ops vector with the
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// vector elements.
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@ -1560,6 +1560,7 @@ void X86TargetLowering::resetOperationActions() {
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
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setTargetDAGCombine(ISD::BUILD_VECTOR);
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if (Subtarget->is64Bit())
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setTargetDAGCombine(ISD::MUL);
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setTargetDAGCombine(ISD::XOR);
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@ -6047,6 +6048,89 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::BITCAST, dl, VT, Select);
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}
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static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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// Try to match a horizontal ADD or SUB.
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if (((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) ||
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((VT == MVT::v8f32 || VT == MVT::v4f64) && Subtarget->hasAVX()) ||
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((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) ||
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((VT == MVT::v8i32 || VT == MVT::v16i16) && Subtarget->hasAVX2())) {
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unsigned NumOperands = N->getNumOperands();
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unsigned Opcode = N->getOperand(0)->getOpcode();
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bool isCommutable = false;
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bool CanFold = false;
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switch (Opcode) {
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default : break;
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case ISD::ADD :
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case ISD::FADD :
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isCommutable = true;
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// FALL-THROUGH
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case ISD::SUB :
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case ISD::FSUB :
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CanFold = true;
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}
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// Verify that operands have the same opcode; also, the opcode can only
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// be either of: ADD, FADD, SUB, FSUB.
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SDValue InVec0, InVec1;
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for (unsigned i = 0, e = NumOperands; i != e && CanFold; ++i) {
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SDValue Op = N->getOperand(i);
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CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
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if (!CanFold)
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break;
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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// Try to match the following pattern:
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// (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
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CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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Op0.getOperand(0) == Op1.getOperand(0) &&
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isa<ConstantSDNode>(Op0.getOperand(1)) &&
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isa<ConstantSDNode>(Op1.getOperand(1)));
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if (!CanFold)
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break;
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unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
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unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
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unsigned ExpectedIndex = (i * 2) % NumOperands;
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if (i == 0)
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InVec0 = Op0.getOperand(0);
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else if (i * 2 == NumOperands)
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InVec1 = Op0.getOperand(0);
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SDValue Expected = (i * 2 < NumOperands) ? InVec0 : InVec1;
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if (I0 == ExpectedIndex)
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CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
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else if (isCommutable && I1 == ExpectedIndex) {
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// Try to see if we can match the following dag sequence:
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// (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
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CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
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}
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}
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if (CanFold) {
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unsigned NewOpcode;
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switch (Opcode) {
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default : llvm_unreachable("Unexpected opcode found!");
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case ISD::ADD : NewOpcode = X86ISD::HADD; break;
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case ISD::FADD : NewOpcode = X86ISD::FHADD; break;
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case ISD::SUB : NewOpcode = X86ISD::HSUB; break;
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case ISD::FSUB : NewOpcode = X86ISD::FHSUB; break;
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}
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return DAG.getNode(NewOpcode, SDLoc(N), VT, InVec0, InVec1);
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}
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}
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return SDValue();
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}
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SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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SDLoc dl(Op);
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@ -20738,6 +20822,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
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case X86ISD::INSERTPS:
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return PerformINSERTPSCombine(N, DAG, Subtarget);
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case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
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}
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return SDValue();
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376
test/CodeGen/X86/haddsub-2.ll
Normal file
376
test/CodeGen/X86/haddsub-2.ll
Normal file
@ -0,0 +1,376 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE3
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; RUN: llc < %s -march=x86-64 -mattr=+sse2,+sse3,+ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSSE3
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; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
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; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
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define <4 x float> @hadd_ps_test1(<4 x float> %A, <4 x float> %B) {
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%vecext = extractelement <4 x float> %A, i32 0
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%vecext1 = extractelement <4 x float> %A, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %A, i32 2
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%vecext3 = extractelement <4 x float> %A, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
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%vecext6 = extractelement <4 x float> %B, i32 0
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%vecext7 = extractelement <4 x float> %B, i32 1
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%add8 = fadd float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
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%vecext10 = extractelement <4 x float> %B, i32 2
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%vecext11 = extractelement <4 x float> %B, i32 3
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%add12 = fadd float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: hadd_ps_test1
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; CHECK: haddps
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; CHECK-NEXT: ret
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define <4 x float> @hadd_ps_test2(<4 x float> %A, <4 x float> %B) {
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%vecext = extractelement <4 x float> %A, i32 2
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%vecext1 = extractelement <4 x float> %A, i32 3
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 1
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%vecext2 = extractelement <4 x float> %A, i32 0
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%vecext3 = extractelement <4 x float> %A, i32 1
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 0
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%vecext6 = extractelement <4 x float> %B, i32 2
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%vecext7 = extractelement <4 x float> %B, i32 3
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%add8 = fadd float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 3
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%vecext10 = extractelement <4 x float> %B, i32 0
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%vecext11 = extractelement <4 x float> %B, i32 1
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%add12 = fadd float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 2
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: hadd_ps_test2
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; CHECK: haddps
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; CHECK-NEXT: ret
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define <4 x float> @hsub_ps_test1(<4 x float> %A, <4 x float> %B) {
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%vecext = extractelement <4 x float> %A, i32 0
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%vecext1 = extractelement <4 x float> %A, i32 1
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%sub = fsub float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %sub, i32 0
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%vecext2 = extractelement <4 x float> %A, i32 2
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%vecext3 = extractelement <4 x float> %A, i32 3
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%sub4 = fsub float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 1
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%vecext6 = extractelement <4 x float> %B, i32 0
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%vecext7 = extractelement <4 x float> %B, i32 1
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%sub8 = fsub float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 2
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%vecext10 = extractelement <4 x float> %B, i32 2
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%vecext11 = extractelement <4 x float> %B, i32 3
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%sub12 = fsub float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 3
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: hsub_ps_test1
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; CHECK: hsubps
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; CHECK-NEXT: ret
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define <4 x float> @hsub_ps_test2(<4 x float> %A, <4 x float> %B) {
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%vecext = extractelement <4 x float> %A, i32 2
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%vecext1 = extractelement <4 x float> %A, i32 3
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%sub = fsub float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %sub, i32 1
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%vecext2 = extractelement <4 x float> %A, i32 0
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%vecext3 = extractelement <4 x float> %A, i32 1
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%sub4 = fsub float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %sub4, i32 0
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%vecext6 = extractelement <4 x float> %B, i32 3
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%vecext7 = extractelement <4 x float> %B, i32 2
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%sub8 = fsub float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %sub8, i32 3
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%vecext10 = extractelement <4 x float> %B, i32 1
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%vecext11 = extractelement <4 x float> %B, i32 0
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%sub12 = fsub float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %sub12, i32 2
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ret <4 x float> %vecinit13
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}
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; CHECK-LABEL: hsub_ps_test2
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; CHECK: hsubps
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; CHECK-NEXT: ret
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define <4 x i32> @phadd_d_test1(<4 x i32> %A, <4 x i32> %B) {
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%vecext = extractelement <4 x i32> %A, i32 0
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%vecext1 = extractelement <4 x i32> %A, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <4 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <4 x i32> %A, i32 2
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%vecext3 = extractelement <4 x i32> %A, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <4 x i32> %vecinit, i32 %add4, i32 1
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%vecext6 = extractelement <4 x i32> %B, i32 0
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%vecext7 = extractelement <4 x i32> %B, i32 1
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%add8 = add i32 %vecext6, %vecext7
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%vecinit9 = insertelement <4 x i32> %vecinit5, i32 %add8, i32 2
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%vecext10 = extractelement <4 x i32> %B, i32 2
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%vecext11 = extractelement <4 x i32> %B, i32 3
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%add12 = add i32 %vecext10, %vecext11
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%vecinit13 = insertelement <4 x i32> %vecinit9, i32 %add12, i32 3
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ret <4 x i32> %vecinit13
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}
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; CHECK-LABEL: phadd_d_test1
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; SSE3-NOT: phaddd
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; SSSE3: phaddd
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; AVX: vphaddd
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; AVX2 vphaddd
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; CHECK: ret
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define <4 x i32> @phadd_d_test2(<4 x i32> %A, <4 x i32> %B) {
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%vecext = extractelement <4 x i32> %A, i32 2
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%vecext1 = extractelement <4 x i32> %A, i32 3
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <4 x i32> undef, i32 %add, i32 1
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%vecext2 = extractelement <4 x i32> %A, i32 0
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%vecext3 = extractelement <4 x i32> %A, i32 1
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <4 x i32> %vecinit, i32 %add4, i32 0
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%vecext6 = extractelement <4 x i32> %B, i32 2
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%vecext7 = extractelement <4 x i32> %B, i32 3
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%add8 = add i32 %vecext6, %vecext7
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%vecinit9 = insertelement <4 x i32> %vecinit5, i32 %add8, i32 3
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%vecext10 = extractelement <4 x i32> %B, i32 0
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%vecext11 = extractelement <4 x i32> %B, i32 1
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%add12 = add i32 %vecext10, %vecext11
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%vecinit13 = insertelement <4 x i32> %vecinit9, i32 %add12, i32 2
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ret <4 x i32> %vecinit13
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}
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; CHECK-LABEL: phadd_d_test2
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; SSE3-NOT: phaddd
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; SSSE3: phaddd
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; AVX: vphaddd
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; AVX2 vphaddd
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; CHECK: ret
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define <4 x i32> @phsub_d_test1(<4 x i32> %A, <4 x i32> %B) {
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%vecext = extractelement <4 x i32> %A, i32 0
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%vecext1 = extractelement <4 x i32> %A, i32 1
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%sub = sub i32 %vecext, %vecext1
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%vecinit = insertelement <4 x i32> undef, i32 %sub, i32 0
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%vecext2 = extractelement <4 x i32> %A, i32 2
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%vecext3 = extractelement <4 x i32> %A, i32 3
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%sub4 = sub i32 %vecext2, %vecext3
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%vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 1
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%vecext6 = extractelement <4 x i32> %B, i32 0
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%vecext7 = extractelement <4 x i32> %B, i32 1
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%sub8 = sub i32 %vecext6, %vecext7
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%vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 2
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%vecext10 = extractelement <4 x i32> %B, i32 2
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%vecext11 = extractelement <4 x i32> %B, i32 3
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%sub12 = sub i32 %vecext10, %vecext11
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%vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 3
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ret <4 x i32> %vecinit13
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}
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; CHECK-LABEL: phsub_d_test1
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; SSE3-NOT: phsubd
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; SSSE3: phsubd
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; AVX: vphsubd
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; AVX2 vphsubd
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; CHECK: ret
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define <4 x i32> @phsub_d_test2(<4 x i32> %A, <4 x i32> %B) {
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%vecext = extractelement <4 x i32> %A, i32 2
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%vecext1 = extractelement <4 x i32> %A, i32 3
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%sub = sub i32 %vecext, %vecext1
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%vecinit = insertelement <4 x i32> undef, i32 %sub, i32 1
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%vecext2 = extractelement <4 x i32> %A, i32 0
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%vecext3 = extractelement <4 x i32> %A, i32 1
|
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%sub4 = sub i32 %vecext2, %vecext3
|
||||
%vecinit5 = insertelement <4 x i32> %vecinit, i32 %sub4, i32 0
|
||||
%vecext6 = extractelement <4 x i32> %B, i32 3
|
||||
%vecext7 = extractelement <4 x i32> %B, i32 2
|
||||
%sub8 = sub i32 %vecext6, %vecext7
|
||||
%vecinit9 = insertelement <4 x i32> %vecinit5, i32 %sub8, i32 3
|
||||
%vecext10 = extractelement <4 x i32> %B, i32 1
|
||||
%vecext11 = extractelement <4 x i32> %B, i32 0
|
||||
%sub12 = sub i32 %vecext10, %vecext11
|
||||
%vecinit13 = insertelement <4 x i32> %vecinit9, i32 %sub12, i32 2
|
||||
ret <4 x i32> %vecinit13
|
||||
}
|
||||
; CHECK-LABEL: phsub_d_test2
|
||||
; SSE3-NOT: phsubd
|
||||
; SSSE3: phsubd
|
||||
; AVX: vphsubd
|
||||
; AVX2 vphsubd
|
||||
; CHECK: ret
|
||||
|
||||
|
||||
define <2 x double> @hadd_pd_test1(<2 x double> %A, <2 x double> %B) {
|
||||
%vecext = extractelement <2 x double> %A, i32 0
|
||||
%vecext1 = extractelement <2 x double> %A, i32 1
|
||||
%add = fadd double %vecext, %vecext1
|
||||
%vecinit = insertelement <2 x double> undef, double %add, i32 0
|
||||
%vecext2 = extractelement <2 x double> %B, i32 0
|
||||
%vecext3 = extractelement <2 x double> %B, i32 1
|
||||
%add2 = fadd double %vecext2, %vecext3
|
||||
%vecinit2 = insertelement <2 x double> %vecinit, double %add2, i32 1
|
||||
ret <2 x double> %vecinit2
|
||||
}
|
||||
; CHECK-LABEL: hadd_pd_test1
|
||||
; CHECK: haddpd
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
define <2 x double> @hadd_pd_test2(<2 x double> %A, <2 x double> %B) {
|
||||
%vecext = extractelement <2 x double> %A, i32 1
|
||||
%vecext1 = extractelement <2 x double> %A, i32 0
|
||||
%add = fadd double %vecext, %vecext1
|
||||
%vecinit = insertelement <2 x double> undef, double %add, i32 0
|
||||
%vecext2 = extractelement <2 x double> %B, i32 1
|
||||
%vecext3 = extractelement <2 x double> %B, i32 0
|
||||
%add2 = fadd double %vecext2, %vecext3
|
||||
%vecinit2 = insertelement <2 x double> %vecinit, double %add2, i32 1
|
||||
ret <2 x double> %vecinit2
|
||||
}
|
||||
; CHECK-LABEL: hadd_pd_test2
|
||||
; CHECK: haddpd
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
define <2 x double> @hsub_pd_test1(<2 x double> %A, <2 x double> %B) {
|
||||
%vecext = extractelement <2 x double> %A, i32 0
|
||||
%vecext1 = extractelement <2 x double> %A, i32 1
|
||||
%sub = fsub double %vecext, %vecext1
|
||||
%vecinit = insertelement <2 x double> undef, double %sub, i32 0
|
||||
%vecext2 = extractelement <2 x double> %B, i32 0
|
||||
%vecext3 = extractelement <2 x double> %B, i32 1
|
||||
%sub2 = fsub double %vecext2, %vecext3
|
||||
%vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 1
|
||||
ret <2 x double> %vecinit2
|
||||
}
|
||||
; CHECK-LABEL: hsub_pd_test1
|
||||
; CHECK: hsubpd
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
define <2 x double> @hsub_pd_test2(<2 x double> %A, <2 x double> %B) {
|
||||
%vecext = extractelement <2 x double> %A, i32 1
|
||||
%vecext1 = extractelement <2 x double> %A, i32 0
|
||||
%sub = fsub double %vecext, %vecext1
|
||||
%vecinit = insertelement <2 x double> undef, double %sub, i32 0
|
||||
%vecext2 = extractelement <2 x double> %B, i32 1
|
||||
%vecext3 = extractelement <2 x double> %B, i32 0
|
||||
%sub2 = fsub double %vecext2, %vecext3
|
||||
%vecinit2 = insertelement <2 x double> %vecinit, double %sub2, i32 1
|
||||
ret <2 x double> %vecinit2
|
||||
}
|
||||
; CHECK-LABEL: hsub_pd_test2
|
||||
; CHECK: hsubpd
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
|
||||
define <4 x double> @avx_vhadd_pd_test(<4 x double> %A, <4 x double> %B) {
|
||||
%vecext = extractelement <4 x double> %A, i32 0
|
||||
%vecext1 = extractelement <4 x double> %A, i32 1
|
||||
%add = fadd double %vecext, %vecext1
|
||||
%vecinit = insertelement <4 x double> undef, double %add, i32 0
|
||||
%vecext2 = extractelement <4 x double> %A, i32 2
|
||||
%vecext3 = extractelement <4 x double> %A, i32 3
|
||||
%add4 = fadd double %vecext2, %vecext3
|
||||
%vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1
|
||||
%vecext6 = extractelement <4 x double> %B, i32 0
|
||||
%vecext7 = extractelement <4 x double> %B, i32 1
|
||||
%add8 = fadd double %vecext6, %vecext7
|
||||
%vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2
|
||||
%vecext10 = extractelement <4 x double> %B, i32 2
|
||||
%vecext11 = extractelement <4 x double> %B, i32 3
|
||||
%add12 = fadd double %vecext10, %vecext11
|
||||
%vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3
|
||||
ret <4 x double> %vecinit13
|
||||
}
|
||||
; CHECK-LABEL: avx_vhadd_pd_test
|
||||
; SSE3: haddpd
|
||||
; SSE3-NEXT: haddpd
|
||||
; SSSE3: haddpd
|
||||
; SSSE3: haddpd
|
||||
; AVX: vhaddpd
|
||||
; AVX2: vhaddpd
|
||||
; CHECK: ret
|
||||
|
||||
|
||||
define <4 x double> @avx_vhsub_pd_test(<4 x double> %A, <4 x double> %B) {
|
||||
%vecext = extractelement <4 x double> %A, i32 0
|
||||
%vecext1 = extractelement <4 x double> %A, i32 1
|
||||
%sub = fsub double %vecext, %vecext1
|
||||
%vecinit = insertelement <4 x double> undef, double %sub, i32 0
|
||||
%vecext2 = extractelement <4 x double> %A, i32 2
|
||||
%vecext3 = extractelement <4 x double> %A, i32 3
|
||||
%sub4 = fsub double %vecext2, %vecext3
|
||||
%vecinit5 = insertelement <4 x double> %vecinit, double %sub4, i32 1
|
||||
%vecext6 = extractelement <4 x double> %B, i32 0
|
||||
%vecext7 = extractelement <4 x double> %B, i32 1
|
||||
%sub8 = fsub double %vecext6, %vecext7
|
||||
%vecinit9 = insertelement <4 x double> %vecinit5, double %sub8, i32 2
|
||||
%vecext10 = extractelement <4 x double> %B, i32 2
|
||||
%vecext11 = extractelement <4 x double> %B, i32 3
|
||||
%sub12 = fsub double %vecext10, %vecext11
|
||||
%vecinit13 = insertelement <4 x double> %vecinit9, double %sub12, i32 3
|
||||
ret <4 x double> %vecinit13
|
||||
}
|
||||
; CHECK-LABEL: avx_vhsub_pd_test
|
||||
; SSE3: hsubpd
|
||||
; SSE3-NEXT: hsubpd
|
||||
; SSSE3: hsubpd
|
||||
; SSSE3-NEXT: hsubpd
|
||||
; AVX: vhsubpd
|
||||
; AVX2: vhsubpd
|
||||
; CHECK: ret
|
||||
|
||||
|
||||
define <8 x i32> @avx2_vphadd_d_test(<8 x i32> %A, <8 x i32> %B) {
|
||||
%vecext = extractelement <8 x i32> %A, i32 0
|
||||
%vecext1 = extractelement <8 x i32> %A, i32 1
|
||||
%add = add i32 %vecext, %vecext1
|
||||
%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
|
||||
%vecext2 = extractelement <8 x i32> %A, i32 2
|
||||
%vecext3 = extractelement <8 x i32> %A, i32 3
|
||||
%add4 = add i32 %vecext2, %vecext3
|
||||
%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 1
|
||||
%vecext6 = extractelement <8 x i32> %A, i32 4
|
||||
%vecext7 = extractelement <8 x i32> %A, i32 5
|
||||
%add8 = add i32 %vecext6, %vecext7
|
||||
%vecinit9 = insertelement <8 x i32> %vecinit5, i32 %add8, i32 2
|
||||
%vecext10 = extractelement <8 x i32> %A, i32 6
|
||||
%vecext11 = extractelement <8 x i32> %A, i32 7
|
||||
%add12 = add i32 %vecext10, %vecext11
|
||||
%vecinit13 = insertelement <8 x i32> %vecinit9, i32 %add12, i32 3
|
||||
%vecext14 = extractelement <8 x i32> %B, i32 0
|
||||
%vecext15 = extractelement <8 x i32> %B, i32 1
|
||||
%add16 = add i32 %vecext14, %vecext15
|
||||
%vecinit17 = insertelement <8 x i32> %vecinit13, i32 %add16, i32 4
|
||||
%vecext18 = extractelement <8 x i32> %B, i32 2
|
||||
%vecext19 = extractelement <8 x i32> %B, i32 3
|
||||
%add20 = add i32 %vecext18, %vecext19
|
||||
%vecinit21 = insertelement <8 x i32> %vecinit17, i32 %add20, i32 5
|
||||
%vecext22 = extractelement <8 x i32> %B, i32 4
|
||||
%vecext23 = extractelement <8 x i32> %B, i32 5
|
||||
%add24 = add i32 %vecext22, %vecext23
|
||||
%vecinit25 = insertelement <8 x i32> %vecinit21, i32 %add24, i32 6
|
||||
%vecext26 = extractelement <8 x i32> %B, i32 6
|
||||
%vecext27 = extractelement <8 x i32> %B, i32 7
|
||||
%add28 = add i32 %vecext26, %vecext27
|
||||
%vecinit29 = insertelement <8 x i32> %vecinit25, i32 %add28, i32 7
|
||||
ret <8 x i32> %vecinit29
|
||||
}
|
||||
; CHECK-LABEL: avx2_vphadd_d_test
|
||||
; SSE3-NOT: phaddd
|
||||
; SSSE3: phaddd
|
||||
; SSSE3-NEXT: phaddd
|
||||
; AVX-NOT: vphaddd
|
||||
; AVX2: vphaddd
|
||||
; CHECK: ret
|
||||
|
||||
Loading…
Reference in New Issue
Block a user