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[X86] Use uint8_t instead of unsigned char as it shortens the code and more explicitly reflects the desired size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
64fd08f76f
commit
9be4b732cf
@ -89,7 +89,7 @@ public:
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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unsigned char getVEXRegisterEncoding(const MCInst &MI,
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uint8_t getVEXRegisterEncoding(const MCInst &MI,
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unsigned OpNum) const {
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unsigned SrcReg = MI.getOperand(OpNum).getReg();
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unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
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@ -101,15 +101,14 @@ public:
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return (~SrcRegNum) & 0xf;
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}
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unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
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uint8_t getWriteMaskRegisterEncoding(const MCInst &MI,
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unsigned OpNum) const {
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assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
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"Invalid mask register as write-mask!");
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unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
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return MaskRegNum;
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return GetX86RegEncoding(MI.getOperand(OpNum));
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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}
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@ -129,8 +128,8 @@ public:
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SmallVectorImpl<MCFixup> &Fixups,
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int ImmOffset = 0) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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inline static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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@ -181,7 +180,7 @@ MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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return Value == (int8_t)Value;
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}
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/// isCDisp8 - Return true if this signed displacement fits in a 8-bit
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@ -202,7 +201,7 @@ static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
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if (Value & Mask) // Unaligned offset
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return false;
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Value /= (int)CD8_Scale;
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bool Ret = (Value == (signed char)Value);
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bool Ret = (Value == (int8_t)Value);
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if (Ret)
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CValue = Value;
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@ -612,26 +611,26 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 1: Same as REX_R=0 (must be 1 in 32-bit mode)
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// 0: Same as REX_R=1 (64 bit mode only)
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//
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unsigned char VEX_R = 0x1;
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unsigned char EVEX_R2 = 0x1;
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uint8_t VEX_R = 0x1;
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uint8_t EVEX_R2 = 0x1;
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// VEX_X: equivalent to REX.X, only used when a
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// register is used for index in SIB Byte.
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//
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// 1: Same as REX.X=0 (must be 1 in 32-bit mode)
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// 0: Same as REX.X=1 (64-bit mode only)
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unsigned char VEX_X = 0x1;
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uint8_t VEX_X = 0x1;
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// VEX_B:
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//
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// 1: Same as REX_B=0 (ignored in 32-bit mode)
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// 0: Same as REX_B=1 (64 bit mode only)
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//
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unsigned char VEX_B = 0x1;
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uint8_t VEX_B = 0x1;
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// VEX_W: opcode specific (use like REX.W, or used for
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// opcode extension, or ignored, depending on the opcode byte)
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unsigned char VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
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uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0;
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// VEX_5M (VEX m-mmmmm field):
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//
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@ -643,7 +642,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 0b01000: XOP map select - 08h instructions with imm byte
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// 0b01001: XOP map select - 09h instructions with no imm byte
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// 0b01010: XOP map select - 0Ah instructions with imm dword
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unsigned char VEX_5M;
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uint8_t VEX_5M;
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switch (TSFlags & X86II::OpMapMask) {
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default: llvm_unreachable("Invalid prefix!");
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case X86II::TB: VEX_5M = 0x1; break; // 0F
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@ -656,8 +655,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// VEX_4V (VEX vvvv field): a register specifier
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// (in 1's complement form) or 1111 if unused.
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unsigned char VEX_4V = 0xf;
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unsigned char EVEX_V2 = 0x1;
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uint8_t VEX_4V = 0xf;
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uint8_t EVEX_V2 = 0x1;
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// EVEX_L2/VEX_L (Vector Length):
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//
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@ -666,8 +665,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 0 1: 256-bit vector
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// 1 0: 512-bit vector
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//
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unsigned char VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
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unsigned char EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
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uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0;
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uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0;
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// VEX_PP: opcode extension providing equivalent
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// functionality of a SIMD prefix
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@ -677,7 +676,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 0b10: F3
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// 0b11: F2
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//
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unsigned char VEX_PP;
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uint8_t VEX_PP;
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switch (TSFlags & X86II::OpPrefixMask) {
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default: llvm_unreachable("Invalid op prefix!");
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case X86II::PS: VEX_PP = 0x0; break; // none
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@ -687,19 +686,19 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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}
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// EVEX_U
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unsigned char EVEX_U = 1; // Always '1' so far
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uint8_t EVEX_U = 1; // Always '1' so far
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// EVEX_z
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unsigned char EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
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uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0;
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// EVEX_b
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unsigned char EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
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uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0;
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// EVEX_rc
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unsigned char EVEX_rc = 0;
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uint8_t EVEX_rc = 0;
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// EVEX_aaa
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unsigned char EVEX_aaa = 0;
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uint8_t EVEX_aaa = 0;
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bool EncodeRC = false;
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@ -925,7 +924,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// +-----+ +--------------+ +-------------------+
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// | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
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// +-----+ +--------------+ +-------------------+
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unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
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uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
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// Can we use the 2 byte VEX prefix?
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if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
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@ -1225,7 +1224,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
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else
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EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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if (TSFlags & X86II::Has3DNow0F0FOpcode)
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BaseOpcode = 0x0F; // Weird 3DNow! encoding.
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