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Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-01-05 10:15:49 +00:00
parent 614fe873ce
commit 9bf73516cb
16 changed files with 38 additions and 56 deletions
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3
lib/CodeGen/CodeGenPrepare.cpp
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@ -3970,7 +3970,8 @@ void VectorPromoteHelper::promoteImpl(Instruction *ToBePromoted) {
isa<UndefValue>(Val) ||
canCauseUndefinedBehavior(ToBePromoted, U.getOperandNo()));
} else
assert(0 && "Did you modified shouldPromote and forgot to update this?");
llvm_unreachable("Did you modified shouldPromote and forgot to update "
"this?");
ToBePromoted->setOperand(U.getOperandNo(), NewVal);
}
Transition->removeFromParent();

4
lib/CodeGen/JumpInstrTables.cpp
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@ -117,8 +117,8 @@ bool replaceGlobalValueIndirectUse(GlobalValue *GV, Value *V, Use *U) {
if (!isa<GlobalAlias>(C))
C->replaceUsesOfWithOnConstant(GV, V, U);
} else {
assert(false && "The Use of a Function symbol is neither an instruction nor"
" a constant");
llvm_unreachable("The Use of a Function symbol is neither an instruction "
"nor a constant");
}
return true;

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -9735,7 +9735,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
} else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
} else {
assert(false && "Invalid constant element type");
llvm_unreachable("Invalid constant element type");
}
}

2
lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
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@ -51,7 +51,7 @@ enum ShiftExtendType {
/// getShiftName - Get the string encoding for the shift type.
static inline const char *getShiftExtendName(AArch64_AM::ShiftExtendType ST) {
switch (ST) {
default: assert(false && "unhandled shift type!");
default: llvm_unreachable("unhandled shift type!");
case AArch64_AM::LSL: return "lsl";
case AArch64_AM::LSR: return "lsr";
case AArch64_AM::ASR: return "asr";

4
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
View File

@ -132,7 +132,7 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
int64_t SignedValue = static_cast<int64_t>(Value);
switch (Kind) {
default:
assert(false && "Unknown fixup kind!");
llvm_unreachable("Unknown fixup kind!");
case AArch64::fixup_aarch64_pcrel_adr_imm21:
if (SignedValue > 2097151 || SignedValue < -2097152)
report_fatal_error("fixup value out of range");
@ -239,7 +239,7 @@ bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
MCInst &Res) const {
assert(false && "AArch64AsmBackend::relaxInstruction() unimplemented");
llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
}
bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {

3
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
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@ -437,8 +437,7 @@ AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
return 3;
}
assert(false && "Invalid value for vector shift amount!");
return 0;
llvm_unreachable("Invalid value for vector shift amount!");
}
uint32_t

2
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -891,7 +891,7 @@ PredicateInstruction(MachineInstr *MI,
continue;
}
else {
assert(false && "Unexpected operand type");
llvm_unreachable("Unexpected operand type");
}
}
}

4
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1412,9 +1412,7 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
switch (Inst.getOpcode()) {
default:
assert(0 && "unimplemented expansion");
return true;
default: llvm_unreachable("unimplemented expansion");
case Mips::LoadImm32Reg:
return expandLoadImm(Inst, IDLoc, Instructions);
case Mips::LoadImm64Reg:

4
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
View File

@ -134,8 +134,8 @@ static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
} else if (const MipsMCExpr *ME = dyn_cast<MipsMCExpr>(Expr)) {
ME->print(OS);
return;
} else if (!(SRE = dyn_cast<MCSymbolRefExpr>(Expr)))
assert(false && "Unexpected MCExpr type.");
} else
SRE = cast<MCSymbolRefExpr>(Expr);
MCSymbolRefExpr::VariantKind Kind = SRE->getKind();

6
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -144,7 +144,6 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
/// opcode, e.g. turning BEQ to BNE.
unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
switch (Opc) {
default: llvm_unreachable("Illegal opcode!");
case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
@ -166,8 +165,7 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
}
assert(false && "Implement this function.");
return 0;
llvm_unreachable("Illegal opcode!");
}
static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
@ -288,7 +286,7 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
assert(false && "adjust stack pointer amount exceeded");
llvm_unreachable("adjust stack pointer amount exceeded");
}
/// Adjust SP by Amount bytes.

3
lib/Target/Mips/MipsLongBranch.cpp
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@ -110,8 +110,7 @@ static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
return MO.getMBB();
}
assert(false && "This instruction does not have an MBB operand.");
return nullptr;
llvm_unreachable("This instruction does not have an MBB operand.");
}
// Traverse the list of instructions backwards until a non-debug instruction is

20
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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@ -374,17 +374,15 @@ void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
} else if (isa<PointerType>(Ty)) {
O << ".param .b" << TLI->getPointerTy().getSizeInBits()
<< " func_retval0";
} else {
if ((Ty->getTypeID() == Type::StructTyID) || isa<VectorType>(Ty)) {
unsigned totalsz = TD->getTypeAllocSize(Ty);
unsigned retAlignment = 0;
if (!llvm::getAlign(*F, 0, retAlignment))
retAlignment = TD->getABITypeAlignment(Ty);
O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
<< "]";
} else
assert(false && "Unknown return type");
}
} else if ((Ty->getTypeID() == Type::StructTyID) || isa<VectorType>(Ty)) {
unsigned totalsz = TD->getTypeAllocSize(Ty);
unsigned retAlignment = 0;
if (!llvm::getAlign(*F, 0, retAlignment))
retAlignment = TD->getABITypeAlignment(Ty);
O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
<< "]";
} else
llvm_unreachable("Unknown return type");
} else {
SmallVector<EVT, 16> vtparts;
ComputeValueVTs(*TLI, Ty, vtparts);

16
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -905,16 +905,14 @@ NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
O << ".param .b" << size << " _";
} else if (isa<PointerType>(retTy)) {
O << ".param .b" << getPointerTy().getSizeInBits() << " _";
} else if ((retTy->getTypeID() == Type::StructTyID) ||
isa<VectorType>(retTy)) {
O << ".param .align "
<< retAlignment
<< " .b8 _["
<< getDataLayout()->getTypeAllocSize(retTy) << "]";
} else {
if((retTy->getTypeID() == Type::StructTyID) ||
isa<VectorType>(retTy)) {
O << ".param .align "
<< retAlignment
<< " .b8 _["
<< getDataLayout()->getTypeAllocSize(retTy) << "]";
} else {
assert(false && "Unknown return type");
}
llvm_unreachable("Unknown return type");
}
O << ") ";
}

16
lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
View File

@ -666,6 +666,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
.addImm(7));
switch (AccessSize) {
default: llvm_unreachable("Incorrect access size");
case 1:
break;
case 2: {
@ -682,9 +683,6 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
.addReg(ScratchRegI32)
.addImm(3));
break;
default:
assert(false && "Incorrect access size");
break;
}
EmitInstruction(
@ -715,15 +713,13 @@ void X86AddressSanitizer32::InstrumentMemOperandLarge(
{
MCInst Inst;
switch (AccessSize) {
default: llvm_unreachable("Incorrect access size");
case 8:
Inst.setOpcode(X86::CMP8mi);
break;
case 16:
Inst.setOpcode(X86::CMP16mi);
break;
default:
assert(false && "Incorrect access size");
break;
}
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(
@ -941,6 +937,7 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
.addImm(7));
switch (AccessSize) {
default: llvm_unreachable("Incorrect access size");
case 1:
break;
case 2: {
@ -957,9 +954,6 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
.addReg(ScratchRegI32)
.addImm(3));
break;
default:
assert(false && "Incorrect access size");
break;
}
EmitInstruction(
@ -990,15 +984,13 @@ void X86AddressSanitizer64::InstrumentMemOperandLarge(
{
MCInst Inst;
switch (AccessSize) {
default: llvm_unreachable("Incorrect access size");
case 8:
Inst.setOpcode(X86::CMP8mi);
break;
case 16:
Inst.setOpcode(X86::CMP16mi);
break;
default:
assert(false && "Incorrect access size");
break;
}
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(

3
lib/Target/X86/X86FixupLEAs.cpp
View File

@ -283,6 +283,7 @@ void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
return;
int addrr_opcode, addri_opcode;
switch (opcode) {
default: llvm_unreachable("Unexpected LEA instruction");
case X86::LEA16r:
addrr_opcode = X86::ADD16rr;
addri_opcode = X86::ADD16ri;
@ -296,8 +297,6 @@ void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
addrr_opcode = X86::ADD64rr;
addri_opcode = X86::ADD64ri32;
break;
default:
assert(false && "Unexpected LEA instruction");
}
DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
DEBUG(dbgs() << "FixLEA: Replaced by: ";);

2
lib/Transforms/Instrumentation/ThreadSanitizer.cpp
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@ -422,7 +422,7 @@ bool ThreadSanitizer::instrumentLoadOrStore(Instruction *I) {
static ConstantInt *createOrdering(IRBuilder<> *IRB, AtomicOrdering ord) {
uint32_t v = 0;
switch (ord) {
case NotAtomic: assert(false);
case NotAtomic: llvm_unreachable("unexpected atomic ordering!");
case Unordered: // Fall-through.
case Monotonic: v = 0; break;
// case Consume: v = 1; break; // Not specified yet.