RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-14 09:56:23 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips][msa] copyPhysReg() should not set RegState::Define on result of CTCMSA.

Browse Source 
Summary:
The machine verifier reports 'Explicit operand marked as def' when it is
manually specified even though it agrees with the operand info.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272646 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2016-06-14 09:11:33 +00:00
parent 7845b7dd45
commit 9cea6726d3
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -129,9 +129,12 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
.addReg(DestReg, RegState::ImplicitDefine); .addReg(DestReg, RegState::ImplicitDefine);
return; return;
} else if (Mips::MSACtrlRegClass.contains(DestReg)) {
BuildMI(MBB, I, DL, get(Mips::CTCMSA))
.addReg(DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
} }
else if (Mips::MSACtrlRegClass.contains(DestReg))
Opc = Mips::CTCMSA;
} }
else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
Opc = Mips::FMOV_S; Opc = Mips::FMOV_S;

4
test/CodeGen/Mips/msa/elm_cxcmsa.ll
View File

@ -1,8 +1,8 @@
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format). ; instruction format).
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s ; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind { define i32 @msa_ir_cfcmsa_test() nounwind {
entry: entry: