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[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5
Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218763 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard
parent
7d64681274
commit
9d7038c437
@ -881,8 +881,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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}
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// v8 adds f64 <-> f16 conversion. Before that it should be expanded.
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if (!Subtarget->hasV8Ops()) {
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// FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
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if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
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setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
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}
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@ -906,16 +906,21 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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}
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}
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// ARMv8 implements a lot of rounding-like FP operations.
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if (Subtarget->hasV8Ops()) {
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static MVT RoundingTypes[] = {MVT::f32, MVT::f64};
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for (const auto Ty : RoundingTypes) {
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setOperationAction(ISD::FFLOOR, Ty, Legal);
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setOperationAction(ISD::FCEIL, Ty, Legal);
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setOperationAction(ISD::FROUND, Ty, Legal);
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setOperationAction(ISD::FTRUNC, Ty, Legal);
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setOperationAction(ISD::FNEARBYINT, Ty, Legal);
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setOperationAction(ISD::FRINT, Ty, Legal);
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// FP-ARMv8 implements a lot of rounding-like FP operations.
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if (Subtarget->hasFPARMv8()) {
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FROUND, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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if (!Subtarget->isFPOnlySP()) {
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::f64, Legal);
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setOperationAction(ISD::FROUND, MVT::f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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}
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}
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// We have target-specific dag combine patterns for the following nodes:
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@ -1,4 +1,6 @@
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; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck %s
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; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck --check-prefix=CHECK --check-prefix=DP %s
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; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16,+fp-only-sp | FileCheck --check-prefix=SP %s
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; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabihf -mattr=+fp-armv8,+d16 | FileCheck --check-prefix=DP %s
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; CHECK-LABEL: test1
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; CHECK: vrintm.f32
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@ -9,7 +11,8 @@ entry:
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}
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; CHECK-LABEL: test2
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; CHECK: vrintm.f64
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; SP: b floor
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; DP: vrintm.f64
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define double @test2(double %a) {
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entry:
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%call = call double @floor(double %a) nounwind readnone
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@ -25,7 +28,8 @@ entry:
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}
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; CHECK-LABEL: test4
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; CHECK: vrintp.f64
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; SP: b ceil
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; DP: vrintp.f64
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define double @test4(double %a) {
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entry:
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%call = call double @ceil(double %a) nounwind readnone
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@ -41,7 +45,8 @@ entry:
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}
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; CHECK-LABEL: test6
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; CHECK: vrinta.f64
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; SP: b round
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; DP: vrinta.f64
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define double @test6(double %a) {
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entry:
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%call = call double @round(double %a) nounwind readnone
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@ -57,7 +62,8 @@ entry:
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}
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; CHECK-LABEL: test8
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; CHECK: vrintz.f64
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; SP: b trunc
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; DP: vrintz.f64
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define double @test8(double %a) {
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entry:
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%call = call double @trunc(double %a) nounwind readnone
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@ -73,7 +79,8 @@ entry:
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}
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; CHECK-LABEL: test10
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; CHECK: vrintr.f64
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; SP: b nearbyint
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; DP: vrintr.f64
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define double @test10(double %a) {
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entry:
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%call = call double @nearbyint(double %a) nounwind readnone
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@ -89,7 +96,8 @@ entry:
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}
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; CHECK-LABEL: test12
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; CHECK: vrintx.f64
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; SP: b rint
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; DP: vrintx.f64
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define double @test12(double %a) {
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entry:
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%call = call double @rint(double %a) nounwind readnone
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@ -1,7 +1,9 @@
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
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declare double @llvm.sqrt.f64(double %Val)
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define double @sqrt_d(double %a) {
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@ -133,7 +135,8 @@ declare double @llvm.floor.f64(double %Val)
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define double @floor_d(double %a) {
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; CHECK-LABEL: floor_d:
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; SOFT: {{(bl|b)}} floor
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; HARD: b floor
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; VFP4: b floor
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; FP-ARMv8: vrintm.f64
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%1 = call double @llvm.floor.f64(double %a)
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ret double %1
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}
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@ -142,7 +145,8 @@ declare double @llvm.ceil.f64(double %Val)
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define double @ceil_d(double %a) {
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; CHECK-LABEL: ceil_d:
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; SOFT: {{(bl|b)}} ceil
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; HARD: b ceil
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; VFP4: b ceil
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; FP-ARMv8: vrintp.f64
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%1 = call double @llvm.ceil.f64(double %a)
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ret double %1
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}
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@ -151,7 +155,8 @@ declare double @llvm.trunc.f64(double %Val)
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define double @trunc_d(double %a) {
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; CHECK-LABEL: trunc_d:
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; SOFT: {{(bl|b)}} trunc
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; HARD: b trunc
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; FFP4: b trunc
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; FP-ARMv8: vrintz.f64
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%1 = call double @llvm.trunc.f64(double %a)
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ret double %1
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}
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@ -160,7 +165,8 @@ declare double @llvm.rint.f64(double %Val)
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define double @rint_d(double %a) {
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; CHECK-LABEL: rint_d:
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; SOFT: {{(bl|b)}} rint
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; HARD: b rint
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; VFP4: b rint
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; FP-ARMv8: vrintx.f64
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%1 = call double @llvm.rint.f64(double %a)
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ret double %1
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}
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@ -169,7 +175,8 @@ declare double @llvm.nearbyint.f64(double %Val)
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define double @nearbyint_d(double %a) {
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; CHECK-LABEL: nearbyint_d:
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; SOFT: {{(bl|b)}} nearbyint
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; HARD: b nearbyint
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; VFP4: b nearbyint
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; FP-ARMv8: vrintr.f64
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%1 = call double @llvm.nearbyint.f64(double %a)
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ret double %1
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}
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@ -178,7 +185,8 @@ declare double @llvm.round.f64(double %Val)
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define double @round_d(double %a) {
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; CHECK-LABEL: round_d:
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; SOFT: {{(bl|b)}} round
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; HARD: b round
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; VFP4: b round
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; FP-ARMv8: vrinta.f64
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%1 = call double @llvm.round.f64(double %a)
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ret double %1
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}
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@ -188,9 +196,9 @@ define double @fmuladd_d(double %a, double %b, double %c) {
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; CHECK-LABEL: fmuladd_d:
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; SOFT: bl __aeabi_dmul
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; SOFT: bl __aeabi_dadd
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; NEON: vmul.f64
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; NEON: vadd.f64
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; VFP: vmla.f64
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; VFP4: vmul.f64
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; VFP4: vadd.f64
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; FP-ARMv8: vmla.f64
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%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
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ret double %1
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}
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@ -199,7 +207,8 @@ declare i16 @llvm.convert.to.fp16.f64(double %a)
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define i16 @d_to_h(double %a) {
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; CHECK-LABEL: d_to_h:
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; SOFT: bl __aeabi_d2h
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; HARD: bl __aeabi_d2h
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; VFP4: bl __aeabi_d2h
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; FP-ARMv8: vcvt{{[bt]}}.f16.f64
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%1 = call i16 @llvm.convert.to.fp16.f64(double %a)
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ret i16 %1
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}
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@ -209,10 +218,11 @@ define double @h_to_d(i16 %a) {
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; CHECK-LABEL: h_to_d:
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; NONE: bl __gnu_h2f_ieee
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; NONE: bl __aeabi_f2d
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; SP: vcvtb.f32.f16
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; SP: vcvt{{[bt]}}.f32.f16
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; SP: bl __aeabi_f2d
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; DP: vcvtb.f32.f16
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; DP: vcvt.f64.f32
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; VFPv4: vcvt{{[bt]}}.f32.f16
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; VFPv4: vcvt.f64.f32
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; FP-ARMv8: vcvt{{[bt]}}.f64.f16
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%1 = call double @llvm.convert.from.fp16.f64(i16 %a)
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ret double %1
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}
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@ -1,7 +1,9 @@
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON
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; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-ARMv8 -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -check-prefix=FP-ARMv8 -check-prefix=VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4 -check-prefix=NO-VMLA
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; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8 -check-prefix=VMLA
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declare float @llvm.sqrt.f32(float %Val)
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define float @sqrt_f(float %a) {
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@ -130,7 +132,8 @@ declare float @llvm.floor.f32(float %Val)
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define float @floor_f(float %a) {
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; CHECK-LABEL: floor_f:
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; SOFT: bl floorf
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; HARD: b floorf
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; VFP4: b floorf
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; FP-ARMv8: vrintm.f32
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%1 = call float @llvm.floor.f32(float %a)
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ret float %1
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}
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@ -139,7 +142,8 @@ declare float @llvm.ceil.f32(float %Val)
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define float @ceil_f(float %a) {
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; CHECK-LABEL: ceil_f:
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; SOFT: bl ceilf
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; HARD: b ceilf
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; VFP4: b ceilf
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; FP-ARMv8: vrintp.f32
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%1 = call float @llvm.ceil.f32(float %a)
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ret float %1
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}
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@ -148,7 +152,8 @@ declare float @llvm.trunc.f32(float %Val)
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define float @trunc_f(float %a) {
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; CHECK-LABEL: trunc_f:
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; SOFT: bl truncf
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; HARD: b truncf
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; VFP4: b truncf
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; FP-ARMv8: vrintz.f32
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%1 = call float @llvm.trunc.f32(float %a)
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ret float %1
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}
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@ -157,7 +162,8 @@ declare float @llvm.rint.f32(float %Val)
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define float @rint_f(float %a) {
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; CHECK-LABEL: rint_f:
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; SOFT: bl rintf
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; HARD: b rintf
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; VFP4: b rintf
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; FP-ARMv8: vrintx.f32
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%1 = call float @llvm.rint.f32(float %a)
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ret float %1
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}
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@ -166,7 +172,8 @@ declare float @llvm.nearbyint.f32(float %Val)
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define float @nearbyint_f(float %a) {
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; CHECK-LABEL: nearbyint_f:
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; SOFT: bl nearbyintf
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; HARD: b nearbyintf
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; VFP4: b nearbyintf
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; FP-ARMv8: vrintr.f32
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%1 = call float @llvm.nearbyint.f32(float %a)
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ret float %1
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}
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@ -175,7 +182,8 @@ declare float @llvm.round.f32(float %Val)
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define float @round_f(float %a) {
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; CHECK-LABEL: round_f:
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; SOFT: bl roundf
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; HARD: b roundf
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; VFP4: b roundf
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; FP-ARMv8: vrinta.f32
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%1 = call float @llvm.round.f32(float %a)
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ret float %1
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}
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@ -187,10 +195,9 @@ define float @fmuladd_f(float %a, float %b, float %c) {
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; CHECK-LABEL: fmuladd_f:
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; SOFT: bl __aeabi_fmul
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; SOFT: bl __aeabi_fadd
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; SP: vmla.f32
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; VFP: vmla.f32
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; NEON: vmul.f32
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; NEON: vadd.f32
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; VMLA: vmla.f32
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; NO-VMLA: vmul.f32
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; NO-VMLA: vadd.f32
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%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
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ret float %1
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}
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@ -199,7 +206,7 @@ declare i16 @llvm.convert.to.fp16.f32(float %a)
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define i16 @f_to_h(float %a) {
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; CHECK-LABEL: f_to_h:
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; SOFT: bl __gnu_f2h_ieee
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; HARD: vcvtb.f16.f32
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; HARD: vcvt{{[bt]}}.f16.f32
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%1 = call i16 @llvm.convert.to.fp16.f32(float %a)
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ret i16 %1
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}
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@ -208,7 +215,7 @@ declare float @llvm.convert.from.fp16.f32(i16 %a)
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define float @h_to_f(i16 %a) {
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; CHECK-LABEL: h_to_f:
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; SOFT: bl __gnu_h2f_ieee
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; HARD: vcvtb.f32.f16
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; HARD: vcvt{{[bt]}}.f32.f16
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%1 = call float @llvm.convert.from.fp16.f32(i16 %a)
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ret float %1
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}
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