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Make NEON ld/st pseudo instruction classes take the instruction itinerary as
an argument, so that we can distinguish instructions with the same register classes but different numbers of registers (e.g., vld3 and vld4). Fix some of the non-pseudo NEON ld/st instruction itineraries to reflect the number of registers loaded or stored, not just the opcode name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
c809d90bca
commit
9d84fb3c91
@ -169,21 +169,21 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// Classes for VLD* pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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class VLDQPseudo
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: PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD2, "">;
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class VLDQWBPseudo
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class VLDQPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
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class VLDQWBPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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(ins addrmode6:$addr, am6offset:$offset), itin,
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"$addr.addr = $wb">;
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class VLDQQPseudo
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: PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VLD4, "">;
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class VLDQQWBPseudo
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class VLDQQPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
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class VLDQQWBPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
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(ins addrmode6:$addr, am6offset:$offset), itin,
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"$addr.addr = $wb">;
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class VLDQQQQWBPseudo
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class VLDQQQQWBPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VLD4,
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(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
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"$addr.addr = $wb, $src = $dst">;
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// VLD1 : Vector Load (multiple single elements)
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@ -193,7 +193,7 @@ class VLD1D<bits<4> op7_4, string Dt>
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"vld1", Dt, "\\{$dst\\}, $addr", "", []>;
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class VLD1Q<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr), IIC_VLD1,
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(ins addrmode6:$addr), IIC_VLD2,
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"vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
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def VLD1d8 : VLD1D<0b0000, "8">;
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@ -206,10 +206,10 @@ def VLD1q16 : VLD1Q<0b0100, "16">;
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def VLD1q32 : VLD1Q<0b1000, "32">;
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def VLD1q64 : VLD1Q<0b1100, "64">;
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def VLD1q8Pseudo : VLDQPseudo;
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def VLD1q16Pseudo : VLDQPseudo;
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def VLD1q32Pseudo : VLDQPseudo;
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def VLD1q64Pseudo : VLDQPseudo;
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def VLD1q8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q16Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q32Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q64Pseudo : VLDQPseudo<IIC_VLD2>;
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// ...with address register writeback:
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class VLD1DWB<bits<4> op7_4, string Dt>
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@ -219,7 +219,7 @@ class VLD1DWB<bits<4> op7_4, string Dt>
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"$addr.addr = $wb", []>;
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class VLD1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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"vld1", Dt, "${dst:dregpair}, $addr$offset",
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"$addr.addr = $wb", []>;
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@ -233,19 +233,19 @@ def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
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def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
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def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
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def VLD1q8Pseudo_UPD : VLDQWBPseudo;
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def VLD1q16Pseudo_UPD : VLDQWBPseudo;
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def VLD1q32Pseudo_UPD : VLDQWBPseudo;
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def VLD1q64Pseudo_UPD : VLDQWBPseudo;
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def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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// ...with 3 registers (some of these are only for the disassembler):
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class VLD1D3<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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(ins addrmode6:$addr), IIC_VLD3, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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class VLD1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD3, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
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def VLD1d8T : VLD1D3<0b0000, "8">;
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@ -258,18 +258,18 @@ def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
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def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
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def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
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def VLD1d64TPseudo : VLDQQPseudo;
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def VLD1d64TPseudo_UPD : VLDQQWBPseudo;
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def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD3>;
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def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
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// ...with 4 registers (some of these are only for the disassembler):
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class VLD1D4<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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(ins addrmode6:$addr), IIC_VLD4, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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class VLD1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
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[]>;
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@ -283,8 +283,8 @@ def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
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def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
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def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
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def VLD1d64QPseudo : VLDQQPseudo;
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def VLD1d64QPseudo_UPD : VLDQQWBPseudo;
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def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -294,7 +294,7 @@ class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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class VLD2Q<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD2,
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(ins addrmode6:$addr), IIC_VLD4,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
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@ -305,13 +305,13 @@ def VLD2q8 : VLD2Q<0b0000, "8">;
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def VLD2q16 : VLD2Q<0b0100, "16">;
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def VLD2q32 : VLD2Q<0b1000, "32">;
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def VLD2d8Pseudo : VLDQPseudo;
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def VLD2d16Pseudo : VLDQPseudo;
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def VLD2d32Pseudo : VLDQPseudo;
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def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2q8Pseudo : VLDQQPseudo;
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def VLD2q16Pseudo : VLDQQPseudo;
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def VLD2q32Pseudo : VLDQQPseudo;
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def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD4>;
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// ...with address register writeback:
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class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -322,7 +322,7 @@ class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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class VLD2QWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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@ -334,13 +334,13 @@ def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
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def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
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def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
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def VLD2d8Pseudo_UPD : VLDQWBPseudo;
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def VLD2d16Pseudo_UPD : VLDQWBPseudo;
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def VLD2d32Pseudo_UPD : VLDQWBPseudo;
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def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2q8Pseudo_UPD : VLDQQWBPseudo;
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def VLD2q16Pseudo_UPD : VLDQQWBPseudo;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo;
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def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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// ...with double-spaced registers (for disassembly only):
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def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
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@ -360,9 +360,9 @@ def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
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def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
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def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
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def VLD3d8Pseudo : VLDQQPseudo;
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def VLD3d16Pseudo : VLDQQPseudo;
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def VLD3d32Pseudo : VLDQQPseudo;
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def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
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def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
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def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
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// ...with address register writeback:
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class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -376,9 +376,9 @@ def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
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def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
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def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
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def VLD3d8Pseudo_UPD : VLDQQWBPseudo;
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def VLD3d16Pseudo_UPD : VLDQQWBPseudo;
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def VLD3d32Pseudo_UPD : VLDQQWBPseudo;
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def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
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def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
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def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
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@ -388,14 +388,14 @@ def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
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def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
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def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
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def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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// ...alternate versions to be allocated odd register numbers:
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def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
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// VLD4 : Vector Load (multiple 4-element structures)
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class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -408,9 +408,9 @@ def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
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def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
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def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
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def VLD4d8Pseudo : VLDQQPseudo;
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def VLD4d16Pseudo : VLDQQPseudo;
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def VLD4d32Pseudo : VLDQQPseudo;
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def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
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// ...with address register writeback:
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class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -424,9 +424,9 @@ def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
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def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
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def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
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def VLD4d8Pseudo_UPD : VLDQQWBPseudo;
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def VLD4d16Pseudo_UPD : VLDQQWBPseudo;
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def VLD4d32Pseudo_UPD : VLDQQWBPseudo;
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def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
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@ -436,14 +436,14 @@ def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
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def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
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def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
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def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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// ...alternate versions to be allocated odd register numbers:
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def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo;
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def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
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// Classes for VLD*LN pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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@ -627,19 +627,19 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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// Classes for VST* pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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class VSTQPseudo
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||||
: PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), IIC_VST, "">;
|
||||
class VSTQWBPseudo
|
||||
class VSTQPseudo<InstrItinClass itin>
|
||||
: PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
|
||||
class VSTQWBPseudo<InstrItinClass itin>
|
||||
: PseudoNLdSt<(outs GPR:$wb),
|
||||
(ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
|
||||
(ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
|
||||
"$addr.addr = $wb">;
|
||||
class VSTQQPseudo
|
||||
: PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
|
||||
class VSTQQWBPseudo
|
||||
class VSTQQPseudo<InstrItinClass itin>
|
||||
: PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
|
||||
class VSTQQWBPseudo<InstrItinClass itin>
|
||||
: PseudoNLdSt<(outs GPR:$wb),
|
||||
(ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST,
|
||||
(ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
|
||||
"$addr.addr = $wb">;
|
||||
class VSTQQQQWBPseudo
|
||||
class VSTQQQQWBPseudo<InstrItinClass itin>
|
||||
: PseudoNLdSt<(outs GPR:$wb),
|
||||
(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
|
||||
"$addr.addr = $wb">;
|
||||
@ -663,10 +663,10 @@ def VST1q16 : VST1Q<0b0100, "16">;
|
||||
def VST1q32 : VST1Q<0b1000, "32">;
|
||||
def VST1q64 : VST1Q<0b1100, "64">;
|
||||
|
||||
def VST1q8Pseudo : VSTQPseudo;
|
||||
def VST1q16Pseudo : VSTQPseudo;
|
||||
def VST1q32Pseudo : VSTQPseudo;
|
||||
def VST1q64Pseudo : VSTQPseudo;
|
||||
def VST1q8Pseudo : VSTQPseudo<IIC_VST>;
|
||||
def VST1q16Pseudo : VSTQPseudo<IIC_VST>;
|
||||
def VST1q32Pseudo : VSTQPseudo<IIC_VST>;
|
||||
def VST1q64Pseudo : VSTQPseudo<IIC_VST>;
|
||||
|
||||
// ...with address register writeback:
|
||||
class VST1DWB<bits<4> op7_4, string Dt>
|
||||
@ -688,10 +688,10 @@ def VST1q16_UPD : VST1QWB<0b0100, "16">;
|
||||
def VST1q32_UPD : VST1QWB<0b1000, "32">;
|
||||
def VST1q64_UPD : VST1QWB<0b1100, "64">;
|
||||
|
||||
def VST1q8Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST1q16Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST1q32Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST1q64Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...with 3 registers (some of these are only for the disassembler):
|
||||
class VST1D3<bits<4> op7_4, string Dt>
|
||||
@ -715,8 +715,8 @@ def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
|
||||
def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
|
||||
def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
|
||||
|
||||
def VST1d64TPseudo : VSTQQPseudo;
|
||||
def VST1d64TPseudo_UPD : VSTQQWBPseudo;
|
||||
def VST1d64TPseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...with 4 registers (some of these are only for the disassembler):
|
||||
class VST1D4<bits<4> op7_4, string Dt>
|
||||
@ -741,8 +741,8 @@ def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
|
||||
def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
|
||||
def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
|
||||
|
||||
def VST1d64QPseudo : VSTQQPseudo;
|
||||
def VST1d64QPseudo_UPD : VSTQQWBPseudo;
|
||||
def VST1d64QPseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
|
||||
// VST2 : Vector Store (multiple 2-element structures)
|
||||
class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -763,13 +763,13 @@ def VST2q8 : VST2Q<0b0000, "8">;
|
||||
def VST2q16 : VST2Q<0b0100, "16">;
|
||||
def VST2q32 : VST2Q<0b1000, "32">;
|
||||
|
||||
def VST2d8Pseudo : VSTQPseudo;
|
||||
def VST2d16Pseudo : VSTQPseudo;
|
||||
def VST2d32Pseudo : VSTQPseudo;
|
||||
def VST2d8Pseudo : VSTQPseudo<IIC_VST>;
|
||||
def VST2d16Pseudo : VSTQPseudo<IIC_VST>;
|
||||
def VST2d32Pseudo : VSTQPseudo<IIC_VST>;
|
||||
|
||||
def VST2q8Pseudo : VSTQQPseudo;
|
||||
def VST2q16Pseudo : VSTQQPseudo;
|
||||
def VST2q32Pseudo : VSTQQPseudo;
|
||||
def VST2q8Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST2q16Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST2q32Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
|
||||
// ...with address register writeback:
|
||||
class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -792,13 +792,13 @@ def VST2q8_UPD : VST2QWB<0b0000, "8">;
|
||||
def VST2q16_UPD : VST2QWB<0b0100, "16">;
|
||||
def VST2q32_UPD : VST2QWB<0b1000, "32">;
|
||||
|
||||
def VST2d8Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST2d16Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST2d32Pseudo_UPD : VSTQWBPseudo;
|
||||
def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST>;
|
||||
|
||||
def VST2q8Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST2q16Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST2q32Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...with double-spaced registers (for disassembly only):
|
||||
def VST2b8 : VST2D<0b1001, 0b0000, "8">;
|
||||
@ -818,9 +818,9 @@ def VST3d8 : VST3D<0b0100, 0b0000, "8">;
|
||||
def VST3d16 : VST3D<0b0100, 0b0100, "16">;
|
||||
def VST3d32 : VST3D<0b0100, 0b1000, "32">;
|
||||
|
||||
def VST3d8Pseudo : VSTQQPseudo;
|
||||
def VST3d16Pseudo : VSTQQPseudo;
|
||||
def VST3d32Pseudo : VSTQQPseudo;
|
||||
def VST3d8Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST3d16Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST3d32Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
|
||||
// ...with address register writeback:
|
||||
class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -834,9 +834,9 @@ def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
|
||||
def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
|
||||
def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
|
||||
|
||||
def VST3d8Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST3d16Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST3d32Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...with double-spaced registers (non-updating versions for disassembly only):
|
||||
def VST3q8 : VST3D<0b0101, 0b0000, "8">;
|
||||
@ -846,14 +846,14 @@ def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
|
||||
def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
|
||||
def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
|
||||
|
||||
def VST3q8Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q16Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q32Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...alternate versions to be allocated odd register numbers:
|
||||
def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
|
||||
// VST4 : Vector Store (multiple 4-element structures)
|
||||
class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -866,9 +866,9 @@ def VST4d8 : VST4D<0b0000, 0b0000, "8">;
|
||||
def VST4d16 : VST4D<0b0000, 0b0100, "16">;
|
||||
def VST4d32 : VST4D<0b0000, 0b1000, "32">;
|
||||
|
||||
def VST4d8Pseudo : VSTQQPseudo;
|
||||
def VST4d16Pseudo : VSTQQPseudo;
|
||||
def VST4d32Pseudo : VSTQQPseudo;
|
||||
def VST4d8Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST4d16Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
def VST4d32Pseudo : VSTQQPseudo<IIC_VST>;
|
||||
|
||||
// ...with address register writeback:
|
||||
class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -882,9 +882,9 @@ def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
|
||||
def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
|
||||
def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
|
||||
|
||||
def VST4d8Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST4d16Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST4d32Pseudo_UPD : VSTQQWBPseudo;
|
||||
def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...with double-spaced registers (non-updating versions for disassembly only):
|
||||
def VST4q8 : VST4D<0b0001, 0b0000, "8">;
|
||||
@ -894,14 +894,14 @@ def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
|
||||
def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
|
||||
def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
|
||||
|
||||
def VST4q8Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q16Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q32Pseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
|
||||
// ...alternate versions to be allocated odd register numbers:
|
||||
def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo;
|
||||
def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST>;
|
||||
|
||||
// Classes for VST*LN pseudo-instructions with multi-register operands.
|
||||
// These are expanded to real instructions after register allocation.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user