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[InstCombine] Add a test for altivec load/store intrinsic simplification

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InstCombine has logic to convert aligned Altivec load/store intrinsics into
regular loads and stores. Unfortunately, there seems to be no regression test
covering this behavior. Adding one...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-02-26 14:22:41 +00:00
parent d89ac8f158
commit 9f9a6fd453
1 changed files with 131 additions and 0 deletions
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131
test/Transforms/InstCombine/aligned-altivec.ll Normal file
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; RUN: opt -S -instcombine < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
define <4 x i32> @test1(<4 x i32>* %h) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
; CHECK-LABEL: @test1
; CHECK: @llvm.ppc.altivec.lvx
; CHECK: ret <4 x i32>
%v0 = load <4 x i32>* %h, align 8
%a = add <4 x i32> %v0, %vl
ret <4 x i32> %a
}
define <4 x i32> @test1a(<4 x i32>* align 16 %h) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
; CHECK-LABEL: @test1a
; CHECK-NOT: @llvm.ppc.altivec.lvx
; CHECK: ret <4 x i32>
%v0 = load <4 x i32>* %h, align 8
%a = add <4 x i32> %v0, %vl
ret <4 x i32> %a
}
declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
%v0 = load <4 x i32>* %h, align 8
ret <4 x i32> %v0
; CHECK-LABEL: @test2
; CHECK: @llvm.ppc.altivec.stvx
; CHECK: ret <4 x i32>
}
define <4 x i32> @test2a(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
%v0 = load <4 x i32>* %h, align 8
ret <4 x i32> %v0
; CHECK-LABEL: @test2
; CHECK-NOT: @llvm.ppc.altivec.stvx
; CHECK: ret <4 x i32>
}
declare <4 x i32> @llvm.ppc.altivec.lvxl(i8*) #1
define <4 x i32> @test1l(<4 x i32>* %h) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
; CHECK-LABEL: @test1l
; CHECK: @llvm.ppc.altivec.lvxl
; CHECK: ret <4 x i32>
%v0 = load <4 x i32>* %h, align 8
%a = add <4 x i32> %v0, %vl
ret <4 x i32> %a
}
define <4 x i32> @test1la(<4 x i32>* align 16 %h) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
; CHECK-LABEL: @test1la
; CHECK-NOT: @llvm.ppc.altivec.lvxl
; CHECK: ret <4 x i32>
%v0 = load <4 x i32>* %h, align 8
%a = add <4 x i32> %v0, %vl
ret <4 x i32> %a
}
declare void @llvm.ppc.altivec.stvxl(<4 x i32>, i8*) #0
define <4 x i32> @test2l(<4 x i32>* %h, <4 x i32> %d) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
%v0 = load <4 x i32>* %h, align 8
ret <4 x i32> %v0
; CHECK-LABEL: @test2l
; CHECK: @llvm.ppc.altivec.stvxl
; CHECK: ret <4 x i32>
}
define <4 x i32> @test2la(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
entry:
%h1 = getelementptr <4 x i32>* %h, i64 1
%hv = bitcast <4 x i32>* %h1 to i8*
call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
%v0 = load <4 x i32>* %h, align 8
ret <4 x i32> %v0
; CHECK-LABEL: @test2l
; CHECK-NOT: @llvm.ppc.altivec.stvxl
; CHECK: ret <4 x i32>
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }