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[Power9] Exploit move and splat instructions for build_vector improvement
This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282246 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic
parent
e2c1cbe138
commit
a04f9019ef
@ -328,10 +328,12 @@ void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
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O << (unsigned int)Value;
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}
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// Operands of BUILD_VECTOR are signed and we use this to print operands
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// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
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// print as unsigned.
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void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 255 && "Invalid u8imm argument!");
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unsigned char Value = MI->getOperand(OpNo).getImm();
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O << (unsigned int)Value;
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}
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@ -672,6 +672,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
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}
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if (Subtarget.isISA3_0() && Subtarget.hasDirectMove())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Legal);
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}
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if (Subtarget.hasQPX()) {
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@ -7079,6 +7082,16 @@ static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT,
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return DAG.getNode(ISD::BITCAST, dl, VT, T);
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}
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static bool isNonConstSplatBV(BuildVectorSDNode *BVN, EVT Type) {
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if (BVN->getValueType(0) != Type)
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return false;
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auto OpZero = BVN->getOperand(0);
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for (int i = 1, e = BVN->getNumOperands(); i < e; i++)
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if (BVN->getOperand(i) != OpZero)
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return false;
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return true;
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}
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it. If we CAN select this case, and if it
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// selects to a single instruction, return Op. Otherwise, if we can codegen
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@ -7200,8 +7213,17 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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bool HasAnyUndefs;
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if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
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SplatBitSize > 32)
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SplatBitSize > 32) {
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// We can splat a non-const value on CPU's that implement ISA 3.0
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// in two ways: LXVWSX (load and splat) and MTVSRWS(move and splat).
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auto OpZero = BVN->getOperand(0);
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bool CanLoadAndSplat = OpZero.getOpcode() == ISD::LOAD &&
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BVN->isOnlyUserOf(OpZero.getNode());
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if (Subtarget.isISA3_0() &&
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isNonConstSplatBV(BVN, MVT::v4i32) && !CanLoadAndSplat)
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return Op;
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return SDValue();
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}
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unsigned SplatBits = APSplatBits.getZExtValue();
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unsigned SplatUndef = APSplatUndef.getZExtValue();
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@ -7219,6 +7241,10 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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return Op;
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}
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// We have XXSPLTIB for constant splats one byte wide
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if (Subtarget.isISA3_0() && Op.getValueType() == MVT::v16i8)
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return Op;
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// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
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int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
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(32-SplatBitSize));
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@ -7462,6 +7488,18 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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if (Subtarget.hasVSX()) {
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if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) {
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int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG);
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// If the source for the shuffle is a scalar_to_vector that came from a
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// 32-bit load, it will have used LXVWSX so we don't need to splat again.
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if (Subtarget.isISA3_0() &&
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((isLittleEndian && SplatIdx == 3) ||
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(!isLittleEndian && SplatIdx == 0))) {
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SDValue Src = V1.getOperand(0);
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if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR &&
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Src.getOperand(0).getOpcode() == ISD::LOAD &&
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Src.getOperand(0).hasOneUse())
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return V1;
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}
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SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
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SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
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DAG.getConstant(SplatIdx, dl, MVT::i32));
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@ -1059,6 +1059,13 @@ class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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let Inst{31} = XT{5};
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}
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class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
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let XA = XT;
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let XB = XT;
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}
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class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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@ -312,6 +312,7 @@ def immZExt16 : PatLeaf<(imm), [{
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// field. Used by instructions like 'ori'.
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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def immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
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// imm16Shifted* - These match immediates where the low 16-bits are zero. There
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// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
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@ -767,6 +767,10 @@ let Uses = [RM] in {
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"xxlxor $XT, $XA, $XB", IIC_VecGeneral,
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[(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
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} // isCommutable
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let isCodeGenOnly = 1 in
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def XXLXORz : XX3Form_Zero<60, 154, (outs vsrc:$XT), (ins),
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"xxlxor $XT, $XT, $XT", IIC_VecGeneral,
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[(set v4i32:$XT, (v4i32 immAllZerosV))]>;
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// Permutation Instructions
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def XXMRGHW : XX3Form<60, 18,
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@ -1315,8 +1319,7 @@ let Predicates = [HasDirectMove] in {
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let Predicates = [IsISA3_0, HasDirectMove] in {
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def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
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"mtvsrws $XT, $rA", IIC_VecGeneral,
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[]>;
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"mtvsrws $XT, $rA", IIC_VecGeneral, []>;
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def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
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"mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
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@ -1880,6 +1883,10 @@ def AlignValues {
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dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC);
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}
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// Materialize a zero-vector of long long
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def : Pat<(v2i64 immAllZerosV),
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(v2i64 (XXLXORz))>;
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// The following VSX instructions were introduced in Power ISA 3.0
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def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
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let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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@ -2310,4 +2317,40 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(STXVX $rS, xoaddr:$dst)>;
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def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
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(STXVX $rS, xoaddr:$dst)>;
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def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))),
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(v4i32 (LXVWSX xoaddr:$src))>;
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def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
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(v4f32 (LXVWSX xoaddr:$src))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
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(v4i32 (MTVSRWS $A))>;
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def : Pat<(v16i8 (build_vector immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A)),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
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def : Pat<(v16i8 immAllOnesV),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v8i16 immAllOnesV),
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(v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v4i32 immAllOnesV),
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(v4i32 (XXSPLTIB 255))>;
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def : Pat<(v2i64 immAllOnesV),
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(v2i64 (XXSPLTIB 255))>;
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} // end HasP9Vector, AddedComplexity
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let Predicates = [IsISA3_0, HasDirectMove, IsLittleEndian] in {
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def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(i64 (extractelt v2i64:$A, 0)),
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(i64 (MFVSRLD $A))>;
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}
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let Predicates = [IsISA3_0, HasDirectMove, IsBigEndian] in {
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def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(i64 (extractelt v2i64:$A, 1)),
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(i64 (MFVSRLD $A))>;
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}
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167
test/CodeGen/PowerPC/power9-moves-and-splats.ll
Normal file
167
test/CodeGen/PowerPC/power9-moves-and-splats.ll
Normal file
@ -0,0 +1,167 @@
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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@Globi = external global i32, align 4
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@Globf = external global float, align 4
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define <2 x i64> @test1(i64 %a, i64 %b) {
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entry:
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; CHECK-LABEL: test1
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; CHECK: mtvsrdd 34, 4, 3
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; CHECK-BE-LABEL: test1
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; CHECK-BE: mtvsrdd 34, 3, 4
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%vecins = insertelement <2 x i64> undef, i64 %a, i32 0
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%vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1
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ret <2 x i64> %vecins1
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}
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define i64 @test2(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2
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; CHECK: mfvsrld 3, 34
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%0 = extractelement <2 x i64> %a, i32 0
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ret i64 %0
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}
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define i64 @test3(<2 x i64> %a) {
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entry:
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; CHECK-BE-LABEL: test3
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; CHECK-BE: mfvsrld 3, 34
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%0 = extractelement <2 x i64> %a, i32 1
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ret i64 %0
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}
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define <4 x i32> @test4(i32* nocapture readonly %in) {
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entry:
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; CHECK-LABEL: test4
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; CHECK: lxvwsx 34, 0, 3
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; CHECK-NOT: xxspltw
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; CHECK-BE-LABEL: test4
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; CHECK-BE: lxvwsx 34, 0, 3
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; CHECK-BE-NOT: xxspltw
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%0 = load i32, i32* %in, align 4
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%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
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%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %splat.splat
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}
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define <4 x float> @test5(float* nocapture readonly %in) {
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entry:
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; CHECK-LABEL: test5
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; CHECK: lxvwsx 34, 0, 3
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; CHECK-NOT: xxspltw
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; CHECK-BE-LABEL: test5
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; CHECK-BE: lxvwsx 34, 0, 3
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; CHECK-BE-NOT: xxspltw
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%0 = load float, float* %in, align 4
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%splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %splat.splat
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}
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define <4 x i32> @test6() {
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entry:
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; CHECK-LABEL: test6
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; CHECK: addis
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; CHECK: ld [[TOC:[0-9]+]], .LC0
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; CHECK: lxvwsx 34, 0, 3
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; CHECK-NOT: xxspltw
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; CHECK-BE-LABEL: test6
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; CHECK-BE: addis
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; CHECK-BE: ld [[TOC:[0-9]+]], .LC0
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; CHECK-BE: lxvwsx 34, 0, 3
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; CHECK-BE-NOT: xxspltw
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%0 = load i32, i32* @Globi, align 4
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%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
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%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %splat.splat
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}
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define <4 x float> @test7() {
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entry:
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; CHECK-LABEL: test7
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; CHECK: addis
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; CHECK: ld [[TOC:[0-9]+]], .LC1
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; CHECK: lxvwsx 34, 0, 3
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; CHECK-NOT: xxspltw
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; CHECK-BE-LABEL: test7
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; CHECK-BE: addis
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; CHECK-BE: ld [[TOC:[0-9]+]], .LC1
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; CHECK-BE: lxvwsx 34, 0, 3
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; CHECK-BE-NOT: xxspltw
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%0 = load float, float* @Globf, align 4
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%splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %splat.splat
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}
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define <16 x i8> @test8() {
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entry:
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; CHECK-LABEL: test8
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; CHECK: xxlxor 34, 34, 34
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; CHECK-BE-LABEL: test8
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; CHECK-BE: xxlxor 34, 34, 34
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ret <16 x i8> zeroinitializer
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}
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define <16 x i8> @test9() {
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entry:
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; CHECK-LABEL: test9
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; CHECK: xxspltib 34, 1
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; CHECK-BE-LABEL: test9
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; CHECK-BE: xxspltib 34, 1
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ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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}
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define <16 x i8> @test10() {
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entry:
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; CHECK-LABEL: test10
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; CHECK: xxspltib 34, 127
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; CHECK-BE-LABEL: test10
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; CHECK-BE: xxspltib 34, 127
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ret <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
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}
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define <16 x i8> @test11() {
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entry:
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; CHECK-LABEL: test11
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; CHECK: xxspltib 34, 128
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; CHECK-BE-LABEL: test11
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; CHECK-BE: xxspltib 34, 128
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ret <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
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}
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define <16 x i8> @test12() {
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entry:
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; CHECK-LABEL: test12
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; CHECK: xxspltib 34, 255
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; CHECK-BE-LABEL: test12
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; CHECK-BE: xxspltib 34, 255
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ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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}
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define <16 x i8> @test13() {
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entry:
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; CHECK-LABEL: test13
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; CHECK: xxspltib 34, 129
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; CHECK-BE-LABEL: test13
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; CHECK-BE: xxspltib 34, 129
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ret <16 x i8> <i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127, i8 -127>
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}
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define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test14
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; CHECK: lwz [[LD:[0-9]+]],
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; CHECK: mtvsrws 34, [[LD]]
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; CHECK-BE-LABEL: test14
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; CHECK-BE: lwz [[LD:[0-9]+]],
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; CHECK-BE: mtvsrws 34, [[LD]]
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%0 = load i32, i32* %b, align 4
|
||||
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%1 = add i32 %0, 5
|
||||
store i32 %1, i32* %b, align 4
|
||||
ret <4 x i32> %splat.splat
|
||||
}
|
||||
@ -17,16 +17,16 @@
|
||||
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-LE-NOVSX
|
||||
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-P9 \
|
||||
; RUN: --implicit-check-not xxswapd
|
||||
; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \
|
||||
; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd
|
||||
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \
|
||||
; RUN: --implicit-check-not xxswapd
|
||||
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=pwr9 -mattr=-power9-vector < %s | FileCheck %s \
|
||||
; RUN: -check-prefix=CHECK-LE
|
||||
; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \
|
||||
; RUN: FileCheck %s -check-prefix=CHECK-LE
|
||||
|
||||
@x = common global <1 x i128> zeroinitializer, align 16
|
||||
@y = common global <1 x i128> zeroinitializer, align 16
|
||||
@ -55,8 +55,10 @@ define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
|
||||
; CHECK-LE: blr
|
||||
|
||||
; CHECK-P9-LABEL: @v1i128_increment_by_one
|
||||
; CHECK-P9: lxvx
|
||||
; CHECK-P9: vadduqm 2, 2, 3
|
||||
; CHECK-P9-DAG: li [[R1:r[0-9]+]], 1
|
||||
; CHECK-P9-DAG: li [[R2:r[0-9]+]], 0
|
||||
; CHECK-P9: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
|
||||
; CHECK-P9: vadduqm v2, v2, [[V1]]
|
||||
; CHECK-P9: blr
|
||||
|
||||
; CHECK-BE-LABEL: @v1i128_increment_by_one
|
||||
@ -232,8 +234,8 @@ define <1 x i128> @call_v1i128_increment_by_val() nounwind {
|
||||
; CHECK-LE: blr
|
||||
|
||||
; CHECK-P9-LABEL: @call_v1i128_increment_by_val
|
||||
; CHECK-P9-DAG: lxvx 34
|
||||
; CHECK-P9-DAG: lxvx 35
|
||||
; CHECK-P9-DAG: lxvx v2
|
||||
; CHECK-P9-DAG: lxvx v3
|
||||
; CHECK-P9: bl v1i128_increment_by_val
|
||||
; CHECK-P9: blr
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user