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AVX-512: cvtusi2ss/d intrinsics.
Change builtin function name and signature ( add third parameter - rounding mode ). Added tests for intrinsics. Differential Revision: http://reviews.llvm.org/D10473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Igor Breger
parent
b7742df420
commit
a066970605
@ -3097,12 +3097,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttss2usi64 : GCCBuiltin<"__builtin_ia32_cvttss2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtusi2ss : GCCBuiltin<"__builtin_ia32_cvtusi2ss">,
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def int_x86_avx512_cvtusi2ss : GCCBuiltin<"__builtin_ia32_cvtusi2ss32">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtusi642ss : GCCBuiltin<"__builtin_ia32_cvtusi642ss">,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtusi642ss : GCCBuiltin<"__builtin_ia32_cvtusi2ss64">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i64_ty], [IntrNoMem]>;
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsd2usi : GCCBuiltin<"__builtin_ia32_cvtsd2usi">,
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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@ -3112,12 +3112,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttsd2usi64 : GCCBuiltin<"__builtin_ia32_cvttsd2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtusi2sd : GCCBuiltin<"__builtin_ia32_cvtusi2sd">,
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def int_x86_avx512_cvtusi2sd : GCCBuiltin<"__builtin_ia32_cvtusi2sd32">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtusi642sd : GCCBuiltin<"__builtin_ia32_cvtusi642sd">,
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def int_x86_avx512_cvtusi642sd : GCCBuiltin<"__builtin_ia32_cvtusi2sd64">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i64_ty], [IntrNoMem]>;
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2ss32 : GCCBuiltin<"__builtin_ia32_cvtsi2ss32">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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@ -3131,7 +3131,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvtsi2sd64 : GCCBuiltin<"__builtin_ia32_cvtsi2sd64">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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// Pack ops.
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@ -4167,25 +4167,45 @@ defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
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// AVX-512 Scalar convert from sign integer to float/double
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//===----------------------------------------------------------------------===//
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multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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X86MemOperand x86memop, string asm> {
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let hasSideEffects = 0 in {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
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multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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X86VectorVTInfo DstVT, X86MemOperand x86memop,
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PatFrag ld_frag, string asm> {
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let hasSideEffects = 0 in {
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def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
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(ins DstVT.FRC:$src1, SrcRC:$src),
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
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EVEX_4V;
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let mayLoad = 1 in
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src),
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let mayLoad = 1 in
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def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
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(ins DstVT.FRC:$src1, x86memop:$src),
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!strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
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EVEX_4V;
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} // hasSideEffects = 0
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} // hasSideEffects = 0
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let isCodeGenOnly = 1 in {
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def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
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(ins DstVT.RC:$src1, SrcRC:$src2),
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!strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set DstVT.RC:$dst,
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(OpNode (DstVT.VT DstVT.RC:$src1),
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SrcRC:$src2,
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(i32 FROUND_CURRENT)))]>, EVEX_4V;
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def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
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(ins DstVT.RC:$src1, x86memop:$src2),
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!strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set DstVT.RC:$dst,
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(OpNode (DstVT.VT DstVT.RC:$src1),
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(ld_frag addr:$src2),
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(i32 FROUND_CURRENT)))]>, EVEX_4V;
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}//isCodeGenOnly = 1
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}
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multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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X86VectorVTInfo DstVT, X86MemOperand x86memop, string asm> {
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X86VectorVTInfo DstVT, string asm> {
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def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
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(ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
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!strconcat(asm,"\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
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!strconcat(asm,
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"\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
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[(set DstVT.RC:$dst,
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(OpNode (DstVT.VT DstVT.RC:$src1),
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SrcRC:$src2,
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@ -4193,20 +4213,26 @@ multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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}
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multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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X86VectorVTInfo DstVT, X86MemOperand x86memop, string asm> {
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defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, x86memop, asm>,
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avx512_vcvtsi<opc, SrcRC, DstVT.FRC, x86memop, asm>, VEX_LIG;
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X86VectorVTInfo DstVT, X86MemOperand x86memop,
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PatFrag ld_frag, string asm> {
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defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
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avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
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VEX_LIG;
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}
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let Predicates = [HasAVX512] in {
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defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
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v4f32x_info, i32mem, "cvtsi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
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v4f32x_info, i64mem, "cvtsi2ss{q}">, XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
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XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
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v2f64x_info, i32mem, "cvtsi2sd{l}">, XD, EVEX_CD8<32, CD8VT1>;
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v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
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XD, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
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v2f64x_info, i64mem, "cvtsi2sd{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
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(VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
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@ -4227,13 +4253,17 @@ def : Pat<(f64 (sint_to_fp GR64:$src)),
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(VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
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defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
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v4f32x_info, i32mem, "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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v4f32x_info, i32mem, loadi32,
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"cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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v4f32x_info, i64mem, "cvtusi2ss{q}">, XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
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XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86SuintToFpRnd, GR32, v2f64x_info,
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i32mem, loadi32, "cvtusi2sd{l}">,
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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v2f64x_info, i64mem, "cvtusi2sd{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
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(VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
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@ -4314,18 +4344,9 @@ let isCodeGenOnly = 1 in {
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int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
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SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
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defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
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int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
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SSE_CVT_Scalar, 0>, XS, EVEX_4V;
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defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
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int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
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SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
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defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
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int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
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SSE_CVT_Scalar, 0>, XD, EVEX_4V;
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defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
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int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
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SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
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} // isCodeGenOnly = 1
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// Convert float/double to signed/unsigned int 32/64 with truncation
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@ -242,10 +242,13 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx2_psubus_b, INTR_TYPE_2OP, X86ISD::SUBUS, 0),
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X86_INTRINSIC_DATA(avx2_psubus_w, INTR_TYPE_2OP, X86ISD::SUBUS, 0),
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X86_INTRINSIC_DATA(avx2_vperm2i128, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtusi2ss, INTR_TYPE_3OP, X86ISD::UINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtusi642sd, INTR_TYPE_3OP, X86ISD::UINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtusi642ss, INTR_TYPE_3OP, X86ISD::UINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_exp2_pd, INTR_TYPE_1OP_MASK_RM, X86ISD::EXP2, 0),
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X86_INTRINSIC_DATA(avx512_exp2_ps, INTR_TYPE_1OP_MASK_RM, X86ISD::EXP2, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_pd_128, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
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@ -2022,6 +2022,8 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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Value *CopyOp, *ConvertOp;
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switch (I.getNumArgOperands()) {
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case 3:
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assert(isa<ConstantInt>(I.getArgOperand(2)) && "Invalid rounding mode");
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case 2:
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CopyOp = I.getArgOperand(0);
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ConvertOp = I.getArgOperand(1);
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@ -176,13 +176,6 @@ define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
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}
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declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
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define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) {
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; CHECK: vcvtusi2sdq {{.*}}encoding: [0x62
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%res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone
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define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
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; CHECK: vcvttsd2si {{.*}}encoding: [0x62
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%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
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@ -2824,6 +2817,103 @@ define <4 x float> @test_x86_avx512_cvtsi2ss64(<4 x float> %a, i64 %b) {
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}
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declare <4 x float> @llvm.x86.avx512.cvtsi2ss64(<4 x float>, i64, i32) nounwind readnone
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define <4 x float> @test_x86_avx512__mm_cvt_roundu32_ss (<4 x float> %a, i32 %b)
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; CHECK-LABEL: test_x86_avx512__mm_cvt_roundu32_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtusi2ssl %edi, {rd-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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{
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%res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 1) ; <<<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_avx512__mm_cvt_roundu32_ss_mem(<4 x float> %a, i32* %ptr)
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; CHECK-LABEL: test_x86_avx512__mm_cvt_roundu32_ss_mem:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: vcvtusi2ssl %eax, {rd-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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{
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%b = load i32, i32* %ptr
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%res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 1) ; <<<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_avx512__mm_cvtu32_ss(<4 x float> %a, i32 %b)
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; CHECK-LABEL: test_x86_avx512__mm_cvtu32_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtusi2ssl %edi, %xmm0, %xmm0
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; CHECK-NEXT: retq
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{
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%res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 4) ; <<<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_avx512__mm_cvtu32_ss_mem(<4 x float> %a, i32* %ptr)
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; CHECK-LABEL: test_x86_avx512__mm_cvtu32_ss_mem:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtusi2ssl (%rdi), %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%b = load i32, i32* %ptr
|
||||
%res = call <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float> %a, i32 %b, i32 4) ; <<<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.cvtusi2ss(<4 x float>, i32, i32) nounwind readnone
|
||||
|
||||
define <4 x float> @_mm_cvt_roundu64_ss (<4 x float> %a, i64 %b)
|
||||
; CHECK-LABEL: _mm_cvt_roundu64_ss:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtusi2ssq %rdi, {rd-sae}, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%res = call <4 x float> @llvm.x86.avx512.cvtusi642ss(<4 x float> %a, i64 %b, i32 1) ; <<<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @_mm_cvtu64_ss(<4 x float> %a, i64 %b)
|
||||
; CHECK-LABEL: _mm_cvtu64_ss:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtusi2ssq %rdi, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%res = call <4 x float> @llvm.x86.avx512.cvtusi642ss(<4 x float> %a, i64 %b, i32 4) ; <<<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.cvtusi642ss(<4 x float>, i64, i32) nounwind readnone
|
||||
|
||||
define <2 x double> @test_x86_avx512_mm_cvtu32_sd(<2 x double> %a, i32 %b)
|
||||
; CHECK-LABEL: test_x86_avx512_mm_cvtu32_sd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtusi2sdl %edi, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%res = call <2 x double> @llvm.x86.avx512.cvtusi2sd(<2 x double> %a, i32 %b) ; <<<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
declare <2 x double> @llvm.x86.avx512.cvtusi2sd(<2 x double>, i32) nounwind readnone
|
||||
|
||||
define <2 x double> @test_x86_avx512_mm_cvtu64_sd(<2 x double> %a, i64 %b)
|
||||
; CHECK-LABEL: test_x86_avx512_mm_cvtu64_sd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtusi2sdq %rdi, {rd-sae}, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a, i64 %b, i32 1) ; <<<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define <2 x double> @test_x86_avx512__mm_cvt_roundu64_sd(<2 x double> %a, i64 %b)
|
||||
; CHECK-LABEL: test_x86_avx512__mm_cvt_roundu64_sd:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtusi2sdq %rdi, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
{
|
||||
%res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a, i64 %b, i32 4) ; <<<2 x double>> [#uses=1]
|
||||
ret <2 x double> %res
|
||||
}
|
||||
declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64, i32) nounwind readnone
|
||||
|
||||
define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {
|
||||
; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user