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AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242023 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
c1a7ff9044
commit
a0a51734cd
@ -728,7 +728,7 @@ namespace ISD {
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/// which do not reference a specific memory location should be less than
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/// this value. Those that do must not be less than this value, and can
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/// be used with SelectionDAG::getMemIntrinsicNode.
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static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+200;
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static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300;
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//===--------------------------------------------------------------------===//
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/// MemIndexedMode enum - This enum defines the load / store indexed
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@ -18899,6 +18899,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
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case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
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case X86ISD::VSHL: return "X86ISD::VSHL";
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@ -19018,6 +19019,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MULHRS: return "X86ISD::MULHRS";
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case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
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case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
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case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
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case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
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}
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return nullptr;
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}
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@ -292,8 +292,8 @@ namespace llvm {
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// Vector FP round.
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VFPROUND,
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// Vector signed integer to double.
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CVTDQ2PD,
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// Vector signed/unsigned integer to double.
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CVTDQ2PD, CVTUDQ2PD,
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// 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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@ -428,6 +428,9 @@ namespace llvm {
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//with rounding mode
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SINT_TO_FP_RND,
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UINT_TO_FP_RND,
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// Vector float/double to signed/unsigned integer.
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FP_TO_SINT_RND, FP_TO_UINT_RND,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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@ -4400,16 +4400,16 @@ def : Pat<(f64 (sint_to_fp GR32:$src)),
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def : Pat<(f64 (sint_to_fp GR64:$src)),
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(VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
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defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
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defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
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v4f32x_info, i32mem, loadi32,
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"cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
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v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
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XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86SuintToFpRnd, GR32, v2f64x_info,
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defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
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i32mem, loadi32, "cvtusi2sd{l}">,
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
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v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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@ -4610,117 +4610,389 @@ def : Pat<(extloadf32 addr:$src),
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def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
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Requires<[HasAVX512]>;
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multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
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RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
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Domain d> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstRC:$dst,
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(OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
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def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
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!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
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[], d>, EVEX, EVEX_B, EVEX_RC;
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let mayLoad = 1 in
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def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstRC:$dst,
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(OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
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} // hasSideEffects = 0
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//===----------------------------------------------------------------------===//
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// AVX-512 Vector convert from signed/unsigned integer to float/double
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// and from float/double to signed/unsigned integer
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//===----------------------------------------------------------------------===//
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multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNode,
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string Broadcast = _.BroadcastStr,
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string Alias = ""> {
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defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _Src.RC:$src), OpcodeStr, "$src", "$src",
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(_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
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defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
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(_.VT (OpNode (_Src.VT
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(bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
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defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _Src.MemOp:$src), OpcodeStr,
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"${src}"##Broadcast, "${src}"##Broadcast,
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(_.VT (OpNode (_Src.VT
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(X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
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))>, EVEX, EVEX_B;
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}
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// Coversion with SAE - suppress all exceptions
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multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNodeRnd> {
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defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _Src.RC:$src), OpcodeStr,
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"{sae}, $src", "$src, {sae}",
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(_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
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(i32 FROUND_NO_EXC)))>,
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EVEX, EVEX_B;
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}
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multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
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RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
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X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
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Domain d> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstRC:$dst,
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(OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
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let mayLoad = 1 in
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def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstRC:$dst,
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(OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
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} // hasSideEffects = 0
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// Conversion with rounding control (RC)
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multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNodeRnd> {
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defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
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"$rc, $src", "$src, $rc",
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(_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
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EVEX, EVEX_B, EVEX_RC;
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}
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defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
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loadv8f64, f512mem, v8f32, v8f64,
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SSEPackedSingle>, EVEX_V512, VEX_W, PD,
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EVEX_CD8<64, CD8VF>;
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// Extend Float to Double
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multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
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avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
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X86vfpextRnd>, EVEX_V512;
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}
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
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X86vfpext, "{1to2}">, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
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EVEX_V256;
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}
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}
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// Truncate Double to Float
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multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
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X86vfproundRnd>, EVEX_V512;
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}
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
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X86vfpround, "{1to2}", "{x}">, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
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"{1to4}", "{y}">, EVEX_V256;
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}
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}
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defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
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VEX_W, PD, EVEX_CD8<64, CD8VF>;
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defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
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PS, EVEX_CD8<32, CD8VH>;
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defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
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loadv4f64, f256mem, v8f64, v8f32,
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SSEPackedDouble>, EVEX_V512, PS,
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EVEX_CD8<32, CD8VH>;
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def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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(VCVTPS2PDZrm addr:$src)>;
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def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
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(bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
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(VCVTPD2PSZrr VR512:$src)>;
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let Predicates = [HasVLX] in {
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def : Pat<(v4f64 (extloadv4f32 addr:$src)),
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(VCVTPS2PDZ256rm addr:$src)>;
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}
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def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
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(bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
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(VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
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// Convert Signed/Unsigned Doubleword to Double
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multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode OpNode128> {
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// No rounding in this op
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let Predicates = [HasAVX512] in
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
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EVEX_V512;
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//===----------------------------------------------------------------------===//
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// AVX-512 Vector convert from sign integer to float/double
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
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OpNode128, "{1to2}">, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
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EVEX_V256;
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}
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}
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defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
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loadv8i64, i512mem, v16f32, v16i32,
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SSEPackedSingle>, EVEX_V512, PS,
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EVEX_CD8<32, CD8VF>;
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// Convert Signed/Unsigned Doubleword to Float
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multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
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OpNodeRnd>, EVEX_V512;
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defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
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loadv4i64, i256mem, v8f64, v8i32,
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SSEPackedDouble>, EVEX_V512, XS,
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
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EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
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EVEX_V256;
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}
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}
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// Convert Float to Signed/Unsigned Doubleword with truncation
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multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
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SDNode OpNode, SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
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avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
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OpNodeRnd>, EVEX_V512;
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}
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
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EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
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EVEX_V256;
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}
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}
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// Convert Float to Signed/Unsigned Doubleword
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multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
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SDNode OpNode, SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
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OpNodeRnd>, EVEX_V512;
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}
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
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EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
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EVEX_V256;
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}
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}
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// Convert Double to Signed/Unsigned Doubleword with truncation
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multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
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SDNode OpNode, SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
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avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
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OpNodeRnd>, EVEX_V512;
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}
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let Predicates = [HasVLX] in {
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// we need "x"/"y" suffixes in order to distinguish between 128 and 256
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// memory forms of these instructions in Asm Parcer. They have the same
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
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"{1to2}", "{x}">, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
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"{1to4}", "{y}">, EVEX_V256;
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}
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}
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// Convert Double to Signed/Unsigned Doubleword
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multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
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SDNode OpNode, SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
|
||||
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasVLX] in {
|
||||
// we need "x"/"y" suffixes in order to distinguish between 128 and 256
|
||||
// memory forms of these instructions in Asm Parcer. They have the same
|
||||
// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
|
||||
// due to the same reason.
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
|
||||
"{1to2}", "{x}">, EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
|
||||
"{1to4}", "{y}">, EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Double to Signed/Unsigned Quardword
|
||||
multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
|
||||
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
|
||||
EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Double to Signed/Unsigned Quardword with truncation
|
||||
multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
|
||||
avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
|
||||
EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Signed/Unsigned Quardword to Double
|
||||
multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
|
||||
avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
|
||||
EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Float to Signed/Unsigned Quardword
|
||||
multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
|
||||
avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
// Explicitly specified broadcast string, since we take only 2 elements
|
||||
// from v4f32x_info source
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
|
||||
"{1to2}">, EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Float to Signed/Unsigned Quardword with truncation
|
||||
multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
|
||||
avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
// Explicitly specified broadcast string, since we take only 2 elements
|
||||
// from v4f32x_info source
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
|
||||
"{1to2}">, EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
|
||||
EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
// Convert Signed/Unsigned Quardword to Float
|
||||
multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode, SDNode OpNodeRnd> {
|
||||
let Predicates = [HasDQI] in {
|
||||
defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
|
||||
avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
|
||||
OpNodeRnd>, EVEX_V512;
|
||||
}
|
||||
let Predicates = [HasDQI, HasVLX] in {
|
||||
// we need "x"/"y" suffixes in order to distinguish between 128 and 256
|
||||
// memory forms of these instructions in Asm Parcer. They have the same
|
||||
// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
|
||||
// due to the same reason.
|
||||
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
|
||||
"{1to2}", "{x}">, EVEX_V128;
|
||||
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
|
||||
"{1to4}", "{y}">, EVEX_V256;
|
||||
}
|
||||
}
|
||||
|
||||
defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
|
||||
EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
|
||||
loadv16f32, f512mem, v16i32, v16f32,
|
||||
SSEPackedSingle>, EVEX_V512, XS,
|
||||
defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
|
||||
X86VSintToFpRnd>,
|
||||
PS, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
|
||||
X86VFpToSintRnd>,
|
||||
XS, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
|
||||
X86VFpToSintRnd>,
|
||||
PD, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
|
||||
X86VFpToUintRnd>, PS,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
|
||||
loadv8f64, f512mem, v8i32, v8f64,
|
||||
SSEPackedDouble>, EVEX_V512, PD, VEX_W,
|
||||
defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
|
||||
X86VFpToUintRnd>, PS, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
|
||||
loadv16f32, f512mem, v16i32, v16f32,
|
||||
SSEPackedSingle>, EVEX_V512, PS,
|
||||
defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
|
||||
XS, EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
|
||||
X86VUintToFpRnd>, XD,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
|
||||
// cvttps2udq (src, 0, mask-all-ones, sae-current)
|
||||
def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
|
||||
(v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
|
||||
(VCVTTPS2UDQZrr VR512:$src)>;
|
||||
defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
|
||||
X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
|
||||
loadv8f64, f512mem, v8i32, v8f64,
|
||||
SSEPackedDouble>, EVEX_V512, PS, VEX_W,
|
||||
defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
|
||||
X86cvtpd2IntRnd>, XD, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
|
||||
// cvttpd2udq (src, 0, mask-all-ones, sae-current)
|
||||
def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
|
||||
(v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
|
||||
(VCVTTPD2UDQZrr VR512:$src)>;
|
||||
defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
|
||||
X86cvtps2UIntRnd>,
|
||||
PS, EVEX_CD8<32, CD8VF>;
|
||||
defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
|
||||
X86cvtpd2UIntRnd>, VEX_W,
|
||||
PS, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
|
||||
loadv4i64, f256mem, v8f64, v8i32,
|
||||
SSEPackedDouble>, EVEX_V512, XS,
|
||||
EVEX_CD8<32, CD8VH>;
|
||||
defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
|
||||
X86cvtpd2IntRnd>, VEX_W,
|
||||
PD, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
|
||||
loadv16i32, f512mem, v16f32, v16i32,
|
||||
SSEPackedSingle>, EVEX_V512, XD,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
|
||||
X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
|
||||
X86cvtpd2UIntRnd>, VEX_W,
|
||||
PD, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
|
||||
X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
|
||||
X86VFpToSlongRnd>, VEX_W,
|
||||
PD, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
|
||||
X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
|
||||
X86VFpToUlongRnd>, VEX_W,
|
||||
PD, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
|
||||
X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
|
||||
|
||||
defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
|
||||
X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
|
||||
X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
|
||||
X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
|
||||
X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
let Predicates = [NoVLX] in {
|
||||
def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
|
||||
(EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
|
||||
(v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
|
||||
@ -4740,67 +5012,8 @@ def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
|
||||
def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
|
||||
(EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
|
||||
(v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
|
||||
|
||||
def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
|
||||
(bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
|
||||
(VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
|
||||
def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
|
||||
(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VCVTDQ2PDZrr VR256X:$src)>;
|
||||
def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
|
||||
(bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
|
||||
(VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
|
||||
def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
|
||||
(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
|
||||
(VCVTUDQ2PDZrr VR256X:$src)>;
|
||||
|
||||
multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
|
||||
RegisterClass DstRC, PatFrag mem_frag,
|
||||
X86MemOperand x86memop, Domain d> {
|
||||
let hasSideEffects = 0 in {
|
||||
def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
|
||||
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
|
||||
[], d>, EVEX;
|
||||
def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
|
||||
!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
|
||||
[], d>, EVEX, EVEX_B, EVEX_RC;
|
||||
let mayLoad = 1 in
|
||||
def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
|
||||
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
|
||||
[], d>, EVEX;
|
||||
} // hasSideEffects = 0
|
||||
}
|
||||
|
||||
defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
|
||||
loadv16f32, f512mem, SSEPackedSingle>, PD,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
|
||||
loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
|
||||
EVEX_V512, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
|
||||
(v16i32 immAllZerosV), (i16 -1), imm:$rc)),
|
||||
(VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
|
||||
|
||||
def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
|
||||
(v8i32 immAllZerosV), (i8 -1), imm:$rc)),
|
||||
(VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
|
||||
|
||||
defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
|
||||
loadv16f32, f512mem, SSEPackedSingle>,
|
||||
PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
|
||||
loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
|
||||
PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
|
||||
(v16i32 immAllZerosV), (i16 -1), imm:$rc)),
|
||||
(VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
|
||||
|
||||
def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
|
||||
(v8i32 immAllZerosV), (i8 -1), imm:$rc)),
|
||||
(VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
|
||||
|
||||
let Predicates = [HasAVX512] in {
|
||||
def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
|
||||
(VCVTPD2PSZrm addr:$src)>;
|
||||
|
||||
@ -70,6 +70,9 @@ def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
|
||||
def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
|
||||
SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
|
||||
SDTCisVT<1, v4i32>]>>;
|
||||
def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
|
||||
SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
|
||||
SDTCisVT<1, v4i32>]>>;
|
||||
def X86pshufb : SDNode<"X86ISD::PSHUFB",
|
||||
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<0,2>]>>;
|
||||
@ -361,8 +364,70 @@ def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
|
||||
def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
|
||||
SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
|
||||
|
||||
def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
|
||||
def X86SuintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
|
||||
def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
|
||||
def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
|
||||
|
||||
def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
|
||||
def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
|
||||
|
||||
def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
|
||||
SDTCisInt<2>]>;
|
||||
def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
|
||||
SDTCisInt<2>]>;
|
||||
|
||||
def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
|
||||
SDTCisInt<2>]>;
|
||||
def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
|
||||
SDTCisInt<2>]>;
|
||||
|
||||
// Scalar
|
||||
def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
|
||||
def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
|
||||
|
||||
// Vector with rounding mode
|
||||
|
||||
// cvtt fp-to-int staff
|
||||
def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
|
||||
def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
|
||||
def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
|
||||
def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
|
||||
|
||||
def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
|
||||
def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
|
||||
def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
|
||||
def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
|
||||
|
||||
// cvt fp-to-int staff
|
||||
def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
|
||||
def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
|
||||
def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
|
||||
def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
|
||||
|
||||
// Vector without rounding mode
|
||||
def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
|
||||
def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
|
||||
def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
|
||||
def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
|
||||
|
||||
def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
|
||||
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<0>, SDTCisFP<1>,
|
||||
SDTCisOpSmallerThanOp<1, 0>,
|
||||
SDTCisInt<2>]>>;
|
||||
def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
|
||||
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
|
||||
SDTCisFP<0>, SDTCisFP<1>,
|
||||
SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, f64>,
|
||||
SDTCisInt<2>]>>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SSE Complex Patterns
|
||||
|
||||
@ -406,20 +406,6 @@ define <8 x i64> @test_x86_mask_blend_q_512(i8 %a0, <8 x i64> %a1, <8 x i64> %a2
|
||||
}
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
|
||||
|
||||
define <8 x i32> @test_cvtpd2udq(<8 x double> %a) {
|
||||
;CHECK: vcvtpd2udq {ru-sae}{{.*}}encoding: [0x62,0xf1,0xfc,0x58,0x79,0xc0]
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %a, <8 x i32>zeroinitializer, i8 -1, i32 2)
|
||||
ret <8 x i32>%res
|
||||
}
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
|
||||
|
||||
define <16 x i32> @test_cvtps2udq(<16 x float> %a) {
|
||||
;CHECK: vcvtps2udq {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x79,0xc0]
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %a, <16 x i32>zeroinitializer, i16 -1, i32 1)
|
||||
ret <16 x i32>%res
|
||||
}
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)
|
||||
|
||||
define i16 @test_cmpps(<16 x float> %a, <16 x float> %b) {
|
||||
;CHECK: vcmpleps {sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x18,0xc2,0xc1,0x02]
|
||||
%res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8)
|
||||
@ -434,35 +420,6 @@ declare <8 x i64> @llvm.x86.avx512.mask.blend.q.512(<8 x i64>, <8 x i64>, i8) no
|
||||
}
|
||||
declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
|
||||
|
||||
; cvt intrinsics
|
||||
define <16 x float> @test_cvtdq2ps(<16 x i32> %a) {
|
||||
;CHECK: vcvtdq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7c,0x38,0x5b,0xc0]
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
|
||||
ret <16 x float>%res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32>, <16 x float>, i16, i32)
|
||||
|
||||
define <16 x float> @test_cvtudq2ps(<16 x i32> %a) {
|
||||
;CHECK: vcvtudq2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0x7f,0x38,0x7a,0xc0]
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %a, <16 x float>zeroinitializer, i16 -1, i32 1)
|
||||
ret <16 x float>%res
|
||||
}
|
||||
declare <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32>, <16 x float>, i16, i32)
|
||||
|
||||
define <8 x double> @test_cvtdq2pd(<8 x i32> %a) {
|
||||
;CHECK: vcvtdq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0xe6,0xc0]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
|
||||
ret <8 x double>%res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
define <8 x double> @test_cvtudq2pd(<8 x i32> %a) {
|
||||
;CHECK: vcvtudq2pd {{.*}}encoding: [0x62,0xf1,0x7e,0x48,0x7a,0xc0]
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %a, <8 x double>zeroinitializer, i8 -1)
|
||||
ret <8 x double>%res
|
||||
}
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
; fp min - max
|
||||
define <8 x double> @test_vmaxpd(<8 x double> %a0, <8 x double> %a1) {
|
||||
; CHECK: vmaxpd
|
||||
@ -482,13 +439,6 @@ define <8 x double> @test_vminpd(<8 x double> %a0, <8 x double> %a1) {
|
||||
declare <8 x double> @llvm.x86.avx512.mask.min.pd.512(<8 x double>, <8 x double>,
|
||||
<8 x double>, i8, i32)
|
||||
|
||||
define <8 x float> @test_cvtpd2ps(<8 x double> %a) {
|
||||
;CHECK: vcvtpd2ps {rd-sae}{{.*}}encoding: [0x62,0xf1,0xfd,0x38,0x5a,0xc0]
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %a, <8 x float>zeroinitializer, i8 -1, i32 1)
|
||||
ret <8 x float>%res
|
||||
}
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
|
||||
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32>, <16 x i32>, i16)
|
||||
|
||||
; CHECK-LABEL: @test_int_x86_avx512_mask_pabs_d_512
|
||||
|
||||
@ -12714,6 +12714,138 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
|
||||
// CHECK: encoding: [0x62,0xe2,0x4d,0x58,0x2c,0x9a,0xfc,0xfd,0xff,0xff]
|
||||
vscalefps -516(%rdx){1to16}, %zmm6, %zmm19
|
||||
|
||||
// CHECK: vcvtps2pd %ymm6, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0xee]
|
||||
vcvtps2pd %ymm6, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd %ymm6, %zmm13 {%k3}
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x4b,0x5a,0xee]
|
||||
vcvtps2pd %ymm6, %zmm13 {%k3}
|
||||
|
||||
// CHECK: vcvtps2pd %ymm6, %zmm13 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0xcb,0x5a,0xee]
|
||||
vcvtps2pd %ymm6, %zmm13 {%k3} {z}
|
||||
|
||||
// CHECK: vcvtps2pd {sae}, %ymm6, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x18,0x5a,0xee]
|
||||
vcvtps2pd {sae}, %ymm6, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd (%rcx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0x29]
|
||||
vcvtps2pd (%rcx), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd 291(%rax,%r14,8), %zmm13
|
||||
// CHECK: encoding: [0x62,0x31,0x7c,0x48,0x5a,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2pd 291(%rax,%r14,8), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd (%rcx){1to8}, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x58,0x5a,0x29]
|
||||
vcvtps2pd (%rcx){1to8}, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd 4064(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0x6a,0x7f]
|
||||
vcvtps2pd 4064(%rdx), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd 4096(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0xaa,0x00,0x10,0x00,0x00]
|
||||
vcvtps2pd 4096(%rdx), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd -4096(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0x6a,0x80]
|
||||
vcvtps2pd -4096(%rdx), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd -4128(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x48,0x5a,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vcvtps2pd -4128(%rdx), %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd 508(%rdx){1to8}, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x58,0x5a,0x6a,0x7f]
|
||||
vcvtps2pd 508(%rdx){1to8}, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd 512(%rdx){1to8}, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x58,0x5a,0xaa,0x00,0x02,0x00,0x00]
|
||||
vcvtps2pd 512(%rdx){1to8}, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd -512(%rdx){1to8}, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x58,0x5a,0x6a,0x80]
|
||||
vcvtps2pd -512(%rdx){1to8}, %zmm13
|
||||
|
||||
// CHECK: vcvtps2pd -516(%rdx){1to8}, %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7c,0x58,0x5a,0xaa,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2pd -516(%rdx){1to8}, %zmm13
|
||||
|
||||
// CHECK: vcvtpd2ps %zmm23, %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x48,0x5a,0xef]
|
||||
vcvtpd2ps %zmm23, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps %zmm23, %ymm5 {%k5}
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x4d,0x5a,0xef]
|
||||
vcvtpd2ps %zmm23, %ymm5 {%k5}
|
||||
|
||||
// CHECK: vcvtpd2ps %zmm23, %ymm5 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0xcd,0x5a,0xef]
|
||||
vcvtpd2ps %zmm23, %ymm5 {%k5} {z}
|
||||
|
||||
// CHECK: vcvtpd2ps {rn-sae}, %zmm23, %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x18,0x5a,0xef]
|
||||
vcvtpd2ps {rn-sae}, %zmm23, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps {ru-sae}, %zmm23, %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x58,0x5a,0xef]
|
||||
vcvtpd2ps {ru-sae}, %zmm23, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps {rd-sae}, %zmm23, %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x38,0x5a,0xef]
|
||||
vcvtpd2ps {rd-sae}, %zmm23, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps {rz-sae}, %zmm23, %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x78,0x5a,0xef]
|
||||
vcvtpd2ps {rz-sae}, %zmm23, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps (%rcx), %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x5a,0x29]
|
||||
vcvtpd2ps (%rcx), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps 291(%rax,%r14,8), %ymm5
|
||||
// CHECK: encoding: [0x62,0xb1,0xfd,0x48,0x5a,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2ps 291(%rax,%r14,8), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps (%rcx){1to8}, %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x58,0x5a,0x29]
|
||||
vcvtpd2ps (%rcx){1to8}, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps 8128(%rdx), %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x5a,0x6a,0x7f]
|
||||
vcvtpd2ps 8128(%rdx), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps 8192(%rdx), %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x5a,0xaa,0x00,0x20,0x00,0x00]
|
||||
vcvtpd2ps 8192(%rdx), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps -8192(%rdx), %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x5a,0x6a,0x80]
|
||||
vcvtpd2ps -8192(%rdx), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps -8256(%rdx), %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x5a,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vcvtpd2ps -8256(%rdx), %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps 1016(%rdx){1to8}, %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x58,0x5a,0x6a,0x7f]
|
||||
vcvtpd2ps 1016(%rdx){1to8}, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps 1024(%rdx){1to8}, %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x58,0x5a,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2ps 1024(%rdx){1to8}, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps -1024(%rdx){1to8}, %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x58,0x5a,0x6a,0x80]
|
||||
vcvtpd2ps -1024(%rdx){1to8}, %ymm5
|
||||
|
||||
// CHECK: vcvtpd2ps -1032(%rdx){1to8}, %ymm5
|
||||
// CHECK: encoding: [0x62,0xf1,0xfd,0x58,0x5a,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2ps -1032(%rdx){1to8}, %ymm5
|
||||
|
||||
// CHECK: vfmadd132ss %xmm22, %xmm17, %xmm30
|
||||
// CHECK: encoding: [0x62,0x22,0x75,0x00,0x99,0xf6]
|
||||
vfmadd132ss %xmm22, %xmm17, %xmm30
|
||||
|
||||
@ -1390,3 +1390,520 @@
|
||||
// CHECK: vrangess $123, -516(%rdx), %xmm24, %xmm25
|
||||
// CHECK: encoding: [0x62,0x63,0x3d,0x00,0x51,0x8a,0xfc,0xfd,0xff,0xff,0x7b]
|
||||
vrangess $0x7b,-516(%rdx), %xmm24, %xmm25
|
||||
|
||||
// CHECK: vcvtpd2qq %zmm29, %zmm18
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x48,0x7b,0xd5]
|
||||
vcvtpd2qq %zmm29, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq %zmm29, %zmm18 {%k6}
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x4e,0x7b,0xd5]
|
||||
vcvtpd2qq %zmm29, %zmm18 {%k6}
|
||||
|
||||
// CHECK: vcvtpd2qq %zmm29, %zmm18 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0xce,0x7b,0xd5]
|
||||
vcvtpd2qq %zmm29, %zmm18 {%k6} {z}
|
||||
|
||||
// CHECK: vcvtpd2qq {rn-sae}, %zmm29, %zmm18
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x18,0x7b,0xd5]
|
||||
vcvtpd2qq {rn-sae}, %zmm29, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq {ru-sae}, %zmm29, %zmm18
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x58,0x7b,0xd5]
|
||||
vcvtpd2qq {ru-sae}, %zmm29, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq {rd-sae}, %zmm29, %zmm18
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x38,0x7b,0xd5]
|
||||
vcvtpd2qq {rd-sae}, %zmm29, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq {rz-sae}, %zmm29, %zmm18
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x78,0x7b,0xd5]
|
||||
vcvtpd2qq {rz-sae}, %zmm29, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx), %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7b,0x11]
|
||||
vcvtpd2qq (%rcx), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq 291(%rax,%r14,8), %zmm18
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x7b,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2qq 291(%rax,%r14,8), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx){1to8}, %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x7b,0x11]
|
||||
vcvtpd2qq (%rcx){1to8}, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq 8128(%rdx), %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7b,0x52,0x7f]
|
||||
vcvtpd2qq 8128(%rdx), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq 8192(%rdx), %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7b,0x92,0x00,0x20,0x00,0x00]
|
||||
vcvtpd2qq 8192(%rdx), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq -8192(%rdx), %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7b,0x52,0x80]
|
||||
vcvtpd2qq -8192(%rdx), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq -8256(%rdx), %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x7b,0x92,0xc0,0xdf,0xff,0xff]
|
||||
vcvtpd2qq -8256(%rdx), %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq 1016(%rdx){1to8}, %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x7b,0x52,0x7f]
|
||||
vcvtpd2qq 1016(%rdx){1to8}, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq 1024(%rdx){1to8}, %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x7b,0x92,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2qq 1024(%rdx){1to8}, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq -1024(%rdx){1to8}, %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x7b,0x52,0x80]
|
||||
vcvtpd2qq -1024(%rdx){1to8}, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2qq -1032(%rdx){1to8}, %zmm18
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x7b,0x92,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2qq -1032(%rdx){1to8}, %zmm18
|
||||
|
||||
// CHECK: vcvtpd2uqq %zmm21, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x79,0xf5]
|
||||
vcvtpd2uqq %zmm21, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq %zmm21, %zmm22 {%k5}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x4d,0x79,0xf5]
|
||||
vcvtpd2uqq %zmm21, %zmm22 {%k5}
|
||||
|
||||
// CHECK: vcvtpd2uqq %zmm21, %zmm22 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0xcd,0x79,0xf5]
|
||||
vcvtpd2uqq %zmm21, %zmm22 {%k5} {z}
|
||||
|
||||
// CHECK: vcvtpd2uqq {rn-sae}, %zmm21, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x18,0x79,0xf5]
|
||||
vcvtpd2uqq {rn-sae}, %zmm21, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq {ru-sae}, %zmm21, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x58,0x79,0xf5]
|
||||
vcvtpd2uqq {ru-sae}, %zmm21, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq {rd-sae}, %zmm21, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x38,0x79,0xf5]
|
||||
vcvtpd2uqq {rd-sae}, %zmm21, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq {rz-sae}, %zmm21, %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x78,0x79,0xf5]
|
||||
vcvtpd2uqq {rz-sae}, %zmm21, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x79,0x31]
|
||||
vcvtpd2uqq (%rcx), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 291(%rax,%r14,8), %zmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x48,0x79,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2uqq 291(%rax,%r14,8), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx){1to8}, %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x79,0x31]
|
||||
vcvtpd2uqq (%rcx){1to8}, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 8128(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x79,0x72,0x7f]
|
||||
vcvtpd2uqq 8128(%rdx), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x79,0xb2,0x00,0x20,0x00,0x00]
|
||||
vcvtpd2uqq 8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -8192(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x79,0x72,0x80]
|
||||
vcvtpd2uqq -8192(%rdx), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -8256(%rdx), %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x48,0x79,0xb2,0xc0,0xdf,0xff,0xff]
|
||||
vcvtpd2uqq -8256(%rdx), %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 1016(%rdx){1to8}, %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x79,0x72,0x7f]
|
||||
vcvtpd2uqq 1016(%rdx){1to8}, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 1024(%rdx){1to8}, %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x79,0xb2,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2uqq 1024(%rdx){1to8}, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -1024(%rdx){1to8}, %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x79,0x72,0x80]
|
||||
vcvtpd2uqq -1024(%rdx){1to8}, %zmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -1032(%rdx){1to8}, %zmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x58,0x79,0xb2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2uqq -1032(%rdx){1to8}, %zmm22
|
||||
|
||||
// CHECK: vcvtps2qq %ymm18, %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x48,0x7b,0xe2]
|
||||
vcvtps2qq %ymm18, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq %ymm18, %zmm20 {%k2}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x4a,0x7b,0xe2]
|
||||
vcvtps2qq %ymm18, %zmm20 {%k2}
|
||||
|
||||
// CHECK: vcvtps2qq %ymm18, %zmm20 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0xca,0x7b,0xe2]
|
||||
vcvtps2qq %ymm18, %zmm20 {%k2} {z}
|
||||
|
||||
// CHECK: vcvtps2qq {rn-sae}, %ymm18, %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x18,0x7b,0xe2]
|
||||
vcvtps2qq {rn-sae}, %ymm18, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq {ru-sae}, %ymm18, %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x58,0x7b,0xe2]
|
||||
vcvtps2qq {ru-sae}, %ymm18, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq {rd-sae}, %ymm18, %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x38,0x7b,0xe2]
|
||||
vcvtps2qq {rd-sae}, %ymm18, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq {rz-sae}, %ymm18, %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x78,0x7b,0xe2]
|
||||
vcvtps2qq {rz-sae}, %ymm18, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx), %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7b,0x21]
|
||||
vcvtps2qq (%rcx), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq 291(%rax,%r14,8), %zmm20
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x48,0x7b,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2qq 291(%rax,%r14,8), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx){1to8}, %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x58,0x7b,0x21]
|
||||
vcvtps2qq (%rcx){1to8}, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq 4064(%rdx), %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7b,0x62,0x7f]
|
||||
vcvtps2qq 4064(%rdx), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq 4096(%rdx), %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7b,0xa2,0x00,0x10,0x00,0x00]
|
||||
vcvtps2qq 4096(%rdx), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq -4096(%rdx), %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7b,0x62,0x80]
|
||||
vcvtps2qq -4096(%rdx), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq -4128(%rdx), %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x48,0x7b,0xa2,0xe0,0xef,0xff,0xff]
|
||||
vcvtps2qq -4128(%rdx), %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq 508(%rdx){1to8}, %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x58,0x7b,0x62,0x7f]
|
||||
vcvtps2qq 508(%rdx){1to8}, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq 512(%rdx){1to8}, %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x58,0x7b,0xa2,0x00,0x02,0x00,0x00]
|
||||
vcvtps2qq 512(%rdx){1to8}, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq -512(%rdx){1to8}, %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x58,0x7b,0x62,0x80]
|
||||
vcvtps2qq -512(%rdx){1to8}, %zmm20
|
||||
|
||||
// CHECK: vcvtps2qq -516(%rdx){1to8}, %zmm20
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x58,0x7b,0xa2,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2qq -516(%rdx){1to8}, %zmm20
|
||||
|
||||
// CHECK: vcvtps2uqq %ymm27, %zmm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x48,0x79,0xcb]
|
||||
vcvtps2uqq %ymm27, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq %ymm27, %zmm25 {%k5}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x4d,0x79,0xcb]
|
||||
vcvtps2uqq %ymm27, %zmm25 {%k5}
|
||||
|
||||
// CHECK: vcvtps2uqq %ymm27, %zmm25 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0xcd,0x79,0xcb]
|
||||
vcvtps2uqq %ymm27, %zmm25 {%k5} {z}
|
||||
|
||||
// CHECK: vcvtps2uqq {rn-sae}, %ymm27, %zmm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x18,0x79,0xcb]
|
||||
vcvtps2uqq {rn-sae}, %ymm27, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq {ru-sae}, %ymm27, %zmm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x58,0x79,0xcb]
|
||||
vcvtps2uqq {ru-sae}, %ymm27, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq {rd-sae}, %ymm27, %zmm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x38,0x79,0xcb]
|
||||
vcvtps2uqq {rd-sae}, %ymm27, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq {rz-sae}, %ymm27, %zmm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x78,0x79,0xcb]
|
||||
vcvtps2uqq {rz-sae}, %ymm27, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx), %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x48,0x79,0x09]
|
||||
vcvtps2uqq (%rcx), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq 291(%rax,%r14,8), %zmm25
|
||||
// CHECK: encoding: [0x62,0x21,0x7d,0x48,0x79,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2uqq 291(%rax,%r14,8), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx){1to8}, %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x58,0x79,0x09]
|
||||
vcvtps2uqq (%rcx){1to8}, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq 4064(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x48,0x79,0x4a,0x7f]
|
||||
vcvtps2uqq 4064(%rdx), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq 4096(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x48,0x79,0x8a,0x00,0x10,0x00,0x00]
|
||||
vcvtps2uqq 4096(%rdx), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq -4096(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x48,0x79,0x4a,0x80]
|
||||
vcvtps2uqq -4096(%rdx), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq -4128(%rdx), %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x48,0x79,0x8a,0xe0,0xef,0xff,0xff]
|
||||
vcvtps2uqq -4128(%rdx), %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq 508(%rdx){1to8}, %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x58,0x79,0x4a,0x7f]
|
||||
vcvtps2uqq 508(%rdx){1to8}, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq 512(%rdx){1to8}, %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x58,0x79,0x8a,0x00,0x02,0x00,0x00]
|
||||
vcvtps2uqq 512(%rdx){1to8}, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq -512(%rdx){1to8}, %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x58,0x79,0x4a,0x80]
|
||||
vcvtps2uqq -512(%rdx){1to8}, %zmm25
|
||||
|
||||
// CHECK: vcvtps2uqq -516(%rdx){1to8}, %zmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x58,0x79,0x8a,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2uqq -516(%rdx){1to8}, %zmm25
|
||||
|
||||
// CHECK: vcvtqq2pd %zmm25, %zmm17
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x48,0xe6,0xc9]
|
||||
vcvtqq2pd %zmm25, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd %zmm25, %zmm17 {%k4}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x4c,0xe6,0xc9]
|
||||
vcvtqq2pd %zmm25, %zmm17 {%k4}
|
||||
|
||||
// CHECK: vcvtqq2pd %zmm25, %zmm17 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0xcc,0xe6,0xc9]
|
||||
vcvtqq2pd %zmm25, %zmm17 {%k4} {z}
|
||||
|
||||
// CHECK: vcvtqq2pd {rn-sae}, %zmm25, %zmm17
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x18,0xe6,0xc9]
|
||||
vcvtqq2pd {rn-sae}, %zmm25, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd {ru-sae}, %zmm25, %zmm17
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x58,0xe6,0xc9]
|
||||
vcvtqq2pd {ru-sae}, %zmm25, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd {rd-sae}, %zmm25, %zmm17
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x38,0xe6,0xc9]
|
||||
vcvtqq2pd {rd-sae}, %zmm25, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd {rz-sae}, %zmm25, %zmm17
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x78,0xe6,0xc9]
|
||||
vcvtqq2pd {rz-sae}, %zmm25, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0xe6,0x09]
|
||||
vcvtqq2pd (%rcx), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd 291(%rax,%r14,8), %zmm17
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x48,0xe6,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2pd 291(%rax,%r14,8), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx){1to8}, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0xe6,0x09]
|
||||
vcvtqq2pd (%rcx){1to8}, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd 8128(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0xe6,0x4a,0x7f]
|
||||
vcvtqq2pd 8128(%rdx), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd 8192(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0xe6,0x8a,0x00,0x20,0x00,0x00]
|
||||
vcvtqq2pd 8192(%rdx), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd -8192(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0xe6,0x4a,0x80]
|
||||
vcvtqq2pd -8192(%rdx), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd -8256(%rdx), %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0xe6,0x8a,0xc0,0xdf,0xff,0xff]
|
||||
vcvtqq2pd -8256(%rdx), %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd 1016(%rdx){1to8}, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0xe6,0x4a,0x7f]
|
||||
vcvtqq2pd 1016(%rdx){1to8}, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd 1024(%rdx){1to8}, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0xe6,0x8a,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2pd 1024(%rdx){1to8}, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd -1024(%rdx){1to8}, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0xe6,0x4a,0x80]
|
||||
vcvtqq2pd -1024(%rdx){1to8}, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2pd -1032(%rdx){1to8}, %zmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0xe6,0x8a,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2pd -1032(%rdx){1to8}, %zmm17
|
||||
|
||||
// CHECK: vcvtqq2ps %zmm27, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x48,0x5b,0xe3]
|
||||
vcvtqq2ps %zmm27, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps %zmm27, %ymm20 {%k5}
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x4d,0x5b,0xe3]
|
||||
vcvtqq2ps %zmm27, %ymm20 {%k5}
|
||||
|
||||
// CHECK: vcvtqq2ps %zmm27, %ymm20 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0xcd,0x5b,0xe3]
|
||||
vcvtqq2ps %zmm27, %ymm20 {%k5} {z}
|
||||
|
||||
// CHECK: vcvtqq2ps {rn-sae}, %zmm27, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x18,0x5b,0xe3]
|
||||
vcvtqq2ps {rn-sae}, %zmm27, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps {ru-sae}, %zmm27, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x58,0x5b,0xe3]
|
||||
vcvtqq2ps {ru-sae}, %zmm27, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps {rd-sae}, %zmm27, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x38,0x5b,0xe3]
|
||||
vcvtqq2ps {rd-sae}, %zmm27, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps {rz-sae}, %zmm27, %ymm20
|
||||
// CHECK: encoding: [0x62,0x81,0xfc,0x78,0x5b,0xe3]
|
||||
vcvtqq2ps {rz-sae}, %zmm27, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps (%rcx), %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x48,0x5b,0x21]
|
||||
vcvtqq2ps (%rcx), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps 291(%rax,%r14,8), %ymm20
|
||||
// CHECK: encoding: [0x62,0xa1,0xfc,0x48,0x5b,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2ps 291(%rax,%r14,8), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps (%rcx){1to8}, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x58,0x5b,0x21]
|
||||
vcvtqq2ps (%rcx){1to8}, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps 8128(%rdx), %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x48,0x5b,0x62,0x7f]
|
||||
vcvtqq2ps 8128(%rdx), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps 8192(%rdx), %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x48,0x5b,0xa2,0x00,0x20,0x00,0x00]
|
||||
vcvtqq2ps 8192(%rdx), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps -8192(%rdx), %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x48,0x5b,0x62,0x80]
|
||||
vcvtqq2ps -8192(%rdx), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps -8256(%rdx), %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x48,0x5b,0xa2,0xc0,0xdf,0xff,0xff]
|
||||
vcvtqq2ps -8256(%rdx), %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps 1016(%rdx){1to8}, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x58,0x5b,0x62,0x7f]
|
||||
vcvtqq2ps 1016(%rdx){1to8}, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps 1024(%rdx){1to8}, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x58,0x5b,0xa2,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2ps 1024(%rdx){1to8}, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps -1024(%rdx){1to8}, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x58,0x5b,0x62,0x80]
|
||||
vcvtqq2ps -1024(%rdx){1to8}, %ymm20
|
||||
|
||||
// CHECK: vcvtqq2ps -1032(%rdx){1to8}, %ymm20
|
||||
// CHECK: encoding: [0x62,0xe1,0xfc,0x58,0x5b,0xa2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2ps -1032(%rdx){1to8}, %ymm20
|
||||
|
||||
// CHECK: vcvtuqq2pd %zmm29, %zmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x48,0x7a,0xed]
|
||||
vcvtuqq2pd %zmm29, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd %zmm29, %zmm21 {%k6}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x4e,0x7a,0xed]
|
||||
vcvtuqq2pd %zmm29, %zmm21 {%k6}
|
||||
|
||||
// CHECK: vcvtuqq2pd %zmm29, %zmm21 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0xce,0x7a,0xed]
|
||||
vcvtuqq2pd %zmm29, %zmm21 {%k6} {z}
|
||||
|
||||
// CHECK: vcvtuqq2pd {rn-sae}, %zmm29, %zmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x18,0x7a,0xed]
|
||||
vcvtuqq2pd {rn-sae}, %zmm29, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd {ru-sae}, %zmm29, %zmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x58,0x7a,0xed]
|
||||
vcvtuqq2pd {ru-sae}, %zmm29, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd {rd-sae}, %zmm29, %zmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x38,0x7a,0xed]
|
||||
vcvtuqq2pd {rd-sae}, %zmm29, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd {rz-sae}, %zmm29, %zmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x78,0x7a,0xed]
|
||||
vcvtuqq2pd {rz-sae}, %zmm29, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx), %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0x7a,0x29]
|
||||
vcvtuqq2pd (%rcx), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd 291(%rax,%r14,8), %zmm21
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x48,0x7a,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtuqq2pd 291(%rax,%r14,8), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx){1to8}, %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0x7a,0x29]
|
||||
vcvtuqq2pd (%rcx){1to8}, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd 8128(%rdx), %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0x7a,0x6a,0x7f]
|
||||
vcvtuqq2pd 8128(%rdx), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd 8192(%rdx), %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0x7a,0xaa,0x00,0x20,0x00,0x00]
|
||||
vcvtuqq2pd 8192(%rdx), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd -8192(%rdx), %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0x7a,0x6a,0x80]
|
||||
vcvtuqq2pd -8192(%rdx), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd -8256(%rdx), %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x48,0x7a,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vcvtuqq2pd -8256(%rdx), %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd 1016(%rdx){1to8}, %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0x7a,0x6a,0x7f]
|
||||
vcvtuqq2pd 1016(%rdx){1to8}, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd 1024(%rdx){1to8}, %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0x7a,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtuqq2pd 1024(%rdx){1to8}, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd -1024(%rdx){1to8}, %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0x7a,0x6a,0x80]
|
||||
vcvtuqq2pd -1024(%rdx){1to8}, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2pd -1032(%rdx){1to8}, %zmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x58,0x7a,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtuqq2pd -1032(%rdx){1to8}, %zmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps %zmm21, %ymm18
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x48,0x7a,0xd5]
|
||||
vcvtuqq2ps %zmm21, %ymm18
|
||||
|
||||
// CHECK: vcvtuqq2ps %zmm21, %ymm18 {%k2}
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x4a,0x7a,0xd5]
|
||||
vcvtuqq2ps %zmm21, %ymm18 {%k2}
|
||||
|
||||
// CHECK: vcvtuqq2ps %zmm21, %ymm18 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0xca,0x7a,0xd5]
|
||||
vcvtuqq2ps %zmm21, %ymm18 {%k2} {z}
|
||||
|
||||
|
||||
@ -2207,3 +2207,900 @@
|
||||
// CHECK: vrangeps $123, -516(%rdx){1to8}, %ymm23, %ymm24
|
||||
// CHECK: encoding: [0x62,0x63,0x45,0x30,0x50,0x82,0xfc,0xfd,0xff,0xff,0x7b]
|
||||
vrangeps $0x7b,-516(%rdx){1to8}, %ymm23, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq %xmm22, %xmm24
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x08,0x7b,0xc6]
|
||||
vcvtpd2qq %xmm22, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq %xmm22, %xmm24 {%k6}
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x0e,0x7b,0xc6]
|
||||
vcvtpd2qq %xmm22, %xmm24 {%k6}
|
||||
|
||||
// CHECK: vcvtpd2qq %xmm22, %xmm24 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x8e,0x7b,0xc6]
|
||||
vcvtpd2qq %xmm22, %xmm24 {%k6} {z}
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx), %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7b,0x01]
|
||||
vcvtpd2qq (%rcx), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq 291(%rax,%r14,8), %xmm24
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x08,0x7b,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2qq 291(%rax,%r14,8), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx){1to2}, %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x7b,0x01]
|
||||
vcvtpd2qq (%rcx){1to2}, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq 2032(%rdx), %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7b,0x42,0x7f]
|
||||
vcvtpd2qq 2032(%rdx), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq 2048(%rdx), %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7b,0x82,0x00,0x08,0x00,0x00]
|
||||
vcvtpd2qq 2048(%rdx), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq -2048(%rdx), %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7b,0x42,0x80]
|
||||
vcvtpd2qq -2048(%rdx), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq -2064(%rdx), %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x08,0x7b,0x82,0xf0,0xf7,0xff,0xff]
|
||||
vcvtpd2qq -2064(%rdx), %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq 1016(%rdx){1to2}, %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x7b,0x42,0x7f]
|
||||
vcvtpd2qq 1016(%rdx){1to2}, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq 1024(%rdx){1to2}, %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x7b,0x82,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2qq 1024(%rdx){1to2}, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq -1024(%rdx){1to2}, %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x7b,0x42,0x80]
|
||||
vcvtpd2qq -1024(%rdx){1to2}, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq -1032(%rdx){1to2}, %xmm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x18,0x7b,0x82,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2qq -1032(%rdx){1to2}, %xmm24
|
||||
|
||||
// CHECK: vcvtpd2qq %ymm27, %ymm24
|
||||
// CHECK: encoding: [0x62,0x01,0xfd,0x28,0x7b,0xc3]
|
||||
vcvtpd2qq %ymm27, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq %ymm27, %ymm24 {%k7}
|
||||
// CHECK: encoding: [0x62,0x01,0xfd,0x2f,0x7b,0xc3]
|
||||
vcvtpd2qq %ymm27, %ymm24 {%k7}
|
||||
|
||||
// CHECK: vcvtpd2qq %ymm27, %ymm24 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0xfd,0xaf,0x7b,0xc3]
|
||||
vcvtpd2qq %ymm27, %ymm24 {%k7} {z}
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x28,0x7b,0x01]
|
||||
vcvtpd2qq (%rcx), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq 291(%rax,%r14,8), %ymm24
|
||||
// CHECK: encoding: [0x62,0x21,0xfd,0x28,0x7b,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2qq 291(%rax,%r14,8), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq (%rcx){1to4}, %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x38,0x7b,0x01]
|
||||
vcvtpd2qq (%rcx){1to4}, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq 4064(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x28,0x7b,0x42,0x7f]
|
||||
vcvtpd2qq 4064(%rdx), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq 4096(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x28,0x7b,0x82,0x00,0x10,0x00,0x00]
|
||||
vcvtpd2qq 4096(%rdx), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq -4096(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x28,0x7b,0x42,0x80]
|
||||
vcvtpd2qq -4096(%rdx), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq -4128(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x28,0x7b,0x82,0xe0,0xef,0xff,0xff]
|
||||
vcvtpd2qq -4128(%rdx), %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq 1016(%rdx){1to4}, %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x38,0x7b,0x42,0x7f]
|
||||
vcvtpd2qq 1016(%rdx){1to4}, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq 1024(%rdx){1to4}, %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x38,0x7b,0x82,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2qq 1024(%rdx){1to4}, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq -1024(%rdx){1to4}, %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x38,0x7b,0x42,0x80]
|
||||
vcvtpd2qq -1024(%rdx){1to4}, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2qq -1032(%rdx){1to4}, %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0xfd,0x38,0x7b,0x82,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2qq -1032(%rdx){1to4}, %ymm24
|
||||
|
||||
// CHECK: vcvtpd2uqq %xmm20, %xmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x08,0x79,0xf4]
|
||||
vcvtpd2uqq %xmm20, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq %xmm20, %xmm22 {%k3}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x0b,0x79,0xf4]
|
||||
vcvtpd2uqq %xmm20, %xmm22 {%k3}
|
||||
|
||||
// CHECK: vcvtpd2uqq %xmm20, %xmm22 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x8b,0x79,0xf4]
|
||||
vcvtpd2uqq %xmm20, %xmm22 {%k3} {z}
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x79,0x31]
|
||||
vcvtpd2uqq (%rcx), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 291(%rax,%r14,8), %xmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x08,0x79,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2uqq 291(%rax,%r14,8), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x18,0x79,0x31]
|
||||
vcvtpd2uqq (%rcx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 2032(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x79,0x72,0x7f]
|
||||
vcvtpd2uqq 2032(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x79,0xb2,0x00,0x08,0x00,0x00]
|
||||
vcvtpd2uqq 2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x79,0x72,0x80]
|
||||
vcvtpd2uqq -2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -2064(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x79,0xb2,0xf0,0xf7,0xff,0xff]
|
||||
vcvtpd2uqq -2064(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 1016(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x18,0x79,0x72,0x7f]
|
||||
vcvtpd2uqq 1016(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq 1024(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x18,0x79,0xb2,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2uqq 1024(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -1024(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x18,0x79,0x72,0x80]
|
||||
vcvtpd2uqq -1024(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq -1032(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x18,0x79,0xb2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2uqq -1032(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtpd2uqq %ymm24, %ymm21
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x28,0x79,0xe8]
|
||||
vcvtpd2uqq %ymm24, %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq %ymm24, %ymm21 {%k6}
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0x2e,0x79,0xe8]
|
||||
vcvtpd2uqq %ymm24, %ymm21 {%k6}
|
||||
|
||||
// CHECK: vcvtpd2uqq %ymm24, %ymm21 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfd,0xae,0x79,0xe8]
|
||||
vcvtpd2uqq %ymm24, %ymm21 {%k6} {z}
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x79,0x29]
|
||||
vcvtpd2uqq (%rcx), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq 291(%rax,%r14,8), %ymm21
|
||||
// CHECK: encoding: [0x62,0xa1,0xfd,0x28,0x79,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtpd2uqq 291(%rax,%r14,8), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq (%rcx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x79,0x29]
|
||||
vcvtpd2uqq (%rcx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq 4064(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x79,0x6a,0x7f]
|
||||
vcvtpd2uqq 4064(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq 4096(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x79,0xaa,0x00,0x10,0x00,0x00]
|
||||
vcvtpd2uqq 4096(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq -4096(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x79,0x6a,0x80]
|
||||
vcvtpd2uqq -4096(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq -4128(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x28,0x79,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vcvtpd2uqq -4128(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq 1016(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x79,0x6a,0x7f]
|
||||
vcvtpd2uqq 1016(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq 1024(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x79,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtpd2uqq 1024(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq -1024(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x79,0x6a,0x80]
|
||||
vcvtpd2uqq -1024(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtpd2uqq -1032(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfd,0x38,0x79,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtpd2uqq -1032(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtps2qq %xmm28, %xmm17
|
||||
// CHECK: encoding: [0x62,0x81,0x7d,0x08,0x7b,0xcc]
|
||||
vcvtps2qq %xmm28, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq %xmm28, %xmm17 {%k4}
|
||||
// CHECK: encoding: [0x62,0x81,0x7d,0x0c,0x7b,0xcc]
|
||||
vcvtps2qq %xmm28, %xmm17 {%k4}
|
||||
|
||||
// CHECK: vcvtps2qq %xmm28, %xmm17 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7d,0x8c,0x7b,0xcc]
|
||||
vcvtps2qq %xmm28, %xmm17 {%k4} {z}
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx), %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7b,0x09]
|
||||
vcvtps2qq (%rcx), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq 291(%rax,%r14,8), %xmm17
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x08,0x7b,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2qq 291(%rax,%r14,8), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx){1to2}, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x18,0x7b,0x09]
|
||||
vcvtps2qq (%rcx){1to2}, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq 1016(%rdx), %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7b,0x4a,0x7f]
|
||||
vcvtps2qq 1016(%rdx), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq 1024(%rdx), %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7b,0x8a,0x00,0x04,0x00,0x00]
|
||||
vcvtps2qq 1024(%rdx), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq -1024(%rdx), %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7b,0x4a,0x80]
|
||||
vcvtps2qq -1024(%rdx), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq -1032(%rdx), %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7b,0x8a,0xf8,0xfb,0xff,0xff]
|
||||
vcvtps2qq -1032(%rdx), %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq 508(%rdx){1to2}, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x18,0x7b,0x4a,0x7f]
|
||||
vcvtps2qq 508(%rdx){1to2}, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq 512(%rdx){1to2}, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x18,0x7b,0x8a,0x00,0x02,0x00,0x00]
|
||||
vcvtps2qq 512(%rdx){1to2}, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq -512(%rdx){1to2}, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x18,0x7b,0x4a,0x80]
|
||||
vcvtps2qq -512(%rdx){1to2}, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq -516(%rdx){1to2}, %xmm17
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x18,0x7b,0x8a,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2qq -516(%rdx){1to2}, %xmm17
|
||||
|
||||
// CHECK: vcvtps2qq %xmm27, %ymm25
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x28,0x7b,0xcb]
|
||||
vcvtps2qq %xmm27, %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq %xmm27, %ymm25 {%k7}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x2f,0x7b,0xcb]
|
||||
vcvtps2qq %xmm27, %ymm25 {%k7}
|
||||
|
||||
// CHECK: vcvtps2qq %xmm27, %ymm25 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0xaf,0x7b,0xcb]
|
||||
vcvtps2qq %xmm27, %ymm25 {%k7} {z}
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx), %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x28,0x7b,0x09]
|
||||
vcvtps2qq (%rcx), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq 291(%rax,%r14,8), %ymm25
|
||||
// CHECK: encoding: [0x62,0x21,0x7d,0x28,0x7b,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2qq 291(%rax,%r14,8), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq (%rcx){1to4}, %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x38,0x7b,0x09]
|
||||
vcvtps2qq (%rcx){1to4}, %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq 2032(%rdx), %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x28,0x7b,0x4a,0x7f]
|
||||
vcvtps2qq 2032(%rdx), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq 2048(%rdx), %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x28,0x7b,0x8a,0x00,0x08,0x00,0x00]
|
||||
vcvtps2qq 2048(%rdx), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq -2048(%rdx), %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x28,0x7b,0x4a,0x80]
|
||||
vcvtps2qq -2048(%rdx), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq -2064(%rdx), %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x28,0x7b,0x8a,0xf0,0xf7,0xff,0xff]
|
||||
vcvtps2qq -2064(%rdx), %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq 508(%rdx){1to4}, %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x38,0x7b,0x4a,0x7f]
|
||||
vcvtps2qq 508(%rdx){1to4}, %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq 512(%rdx){1to4}, %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x38,0x7b,0x8a,0x00,0x02,0x00,0x00]
|
||||
vcvtps2qq 512(%rdx){1to4}, %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq -512(%rdx){1to4}, %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x38,0x7b,0x4a,0x80]
|
||||
vcvtps2qq -512(%rdx){1to4}, %ymm25
|
||||
|
||||
// CHECK: vcvtps2qq -516(%rdx){1to4}, %ymm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x38,0x7b,0x8a,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2qq -516(%rdx){1to4}, %ymm25
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm29, %xmm29
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x08,0x79,0xed]
|
||||
vcvtps2uqq %xmm29, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm29, %xmm29 {%k1}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x09,0x79,0xed]
|
||||
vcvtps2uqq %xmm29, %xmm29 {%k1}
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm29, %xmm29 {%k1} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x7d,0x89,0x79,0xed]
|
||||
vcvtps2uqq %xmm29, %xmm29 {%k1} {z}
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x08,0x79,0x29]
|
||||
vcvtps2uqq (%rcx), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq 291(%rax,%r14,8), %xmm29
|
||||
// CHECK: encoding: [0x62,0x21,0x7d,0x08,0x79,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2uqq 291(%rax,%r14,8), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx){1to2}, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x18,0x79,0x29]
|
||||
vcvtps2uqq (%rcx){1to2}, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq 1016(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x08,0x79,0x6a,0x7f]
|
||||
vcvtps2uqq 1016(%rdx), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq 1024(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x08,0x79,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtps2uqq 1024(%rdx), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq -1024(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x08,0x79,0x6a,0x80]
|
||||
vcvtps2uqq -1024(%rdx), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq -1032(%rdx), %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x08,0x79,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtps2uqq -1032(%rdx), %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq 508(%rdx){1to2}, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x18,0x79,0x6a,0x7f]
|
||||
vcvtps2uqq 508(%rdx){1to2}, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq 512(%rdx){1to2}, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x18,0x79,0xaa,0x00,0x02,0x00,0x00]
|
||||
vcvtps2uqq 512(%rdx){1to2}, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq -512(%rdx){1to2}, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x18,0x79,0x6a,0x80]
|
||||
vcvtps2uqq -512(%rdx){1to2}, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq -516(%rdx){1to2}, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x7d,0x18,0x79,0xaa,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2uqq -516(%rdx){1to2}, %xmm29
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm19, %ymm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x28,0x79,0xfb]
|
||||
vcvtps2uqq %xmm19, %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm19, %ymm23 {%k2}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x2a,0x79,0xfb]
|
||||
vcvtps2uqq %xmm19, %ymm23 {%k2}
|
||||
|
||||
// CHECK: vcvtps2uqq %xmm19, %ymm23 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0xaa,0x79,0xfb]
|
||||
vcvtps2uqq %xmm19, %ymm23 {%k2} {z}
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x28,0x79,0x39]
|
||||
vcvtps2uqq (%rcx), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq 291(%rax,%r14,8), %ymm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x7d,0x28,0x79,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtps2uqq 291(%rax,%r14,8), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq (%rcx){1to4}, %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x38,0x79,0x39]
|
||||
vcvtps2uqq (%rcx){1to4}, %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq 2032(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x28,0x79,0x7a,0x7f]
|
||||
vcvtps2uqq 2032(%rdx), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq 2048(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x28,0x79,0xba,0x00,0x08,0x00,0x00]
|
||||
vcvtps2uqq 2048(%rdx), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq -2048(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x28,0x79,0x7a,0x80]
|
||||
vcvtps2uqq -2048(%rdx), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq -2064(%rdx), %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x28,0x79,0xba,0xf0,0xf7,0xff,0xff]
|
||||
vcvtps2uqq -2064(%rdx), %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq 508(%rdx){1to4}, %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x38,0x79,0x7a,0x7f]
|
||||
vcvtps2uqq 508(%rdx){1to4}, %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq 512(%rdx){1to4}, %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x38,0x79,0xba,0x00,0x02,0x00,0x00]
|
||||
vcvtps2uqq 512(%rdx){1to4}, %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq -512(%rdx){1to4}, %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x38,0x79,0x7a,0x80]
|
||||
vcvtps2uqq -512(%rdx){1to4}, %ymm23
|
||||
|
||||
// CHECK: vcvtps2uqq -516(%rdx){1to4}, %ymm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7d,0x38,0x79,0xba,0xfc,0xfd,0xff,0xff]
|
||||
vcvtps2uqq -516(%rdx){1to4}, %ymm23
|
||||
|
||||
// CHECK: vcvtqq2pd %xmm29, %xmm22
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x08,0xe6,0xf5]
|
||||
vcvtqq2pd %xmm29, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd %xmm29, %xmm22 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x0f,0xe6,0xf5]
|
||||
vcvtqq2pd %xmm29, %xmm22 {%k7}
|
||||
|
||||
// CHECK: vcvtqq2pd %xmm29, %xmm22 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xfe,0x8f,0xe6,0xf5]
|
||||
vcvtqq2pd %xmm29, %xmm22 {%k7} {z}
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0xe6,0x31]
|
||||
vcvtqq2pd (%rcx), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd 291(%rax,%r14,8), %xmm22
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x08,0xe6,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2pd 291(%rax,%r14,8), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0xe6,0x31]
|
||||
vcvtqq2pd (%rcx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd 2032(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0xe6,0x72,0x7f]
|
||||
vcvtqq2pd 2032(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd 2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0xe6,0xb2,0x00,0x08,0x00,0x00]
|
||||
vcvtqq2pd 2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd -2048(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0xe6,0x72,0x80]
|
||||
vcvtqq2pd -2048(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd -2064(%rdx), %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0xe6,0xb2,0xf0,0xf7,0xff,0xff]
|
||||
vcvtqq2pd -2064(%rdx), %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd 1016(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0xe6,0x72,0x7f]
|
||||
vcvtqq2pd 1016(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd 1024(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0xe6,0xb2,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2pd 1024(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd -1024(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0xe6,0x72,0x80]
|
||||
vcvtqq2pd -1024(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd -1032(%rdx){1to2}, %xmm22
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0xe6,0xb2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2pd -1032(%rdx){1to2}, %xmm22
|
||||
|
||||
// CHECK: vcvtqq2pd %ymm20, %ymm21
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x28,0xe6,0xec]
|
||||
vcvtqq2pd %ymm20, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd %ymm20, %ymm21 {%k5}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x2d,0xe6,0xec]
|
||||
vcvtqq2pd %ymm20, %ymm21 {%k5}
|
||||
|
||||
// CHECK: vcvtqq2pd %ymm20, %ymm21 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0xad,0xe6,0xec]
|
||||
vcvtqq2pd %ymm20, %ymm21 {%k5} {z}
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x28,0xe6,0x29]
|
||||
vcvtqq2pd (%rcx), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd 291(%rax,%r14,8), %ymm21
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x28,0xe6,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2pd 291(%rax,%r14,8), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd (%rcx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x38,0xe6,0x29]
|
||||
vcvtqq2pd (%rcx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd 4064(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x28,0xe6,0x6a,0x7f]
|
||||
vcvtqq2pd 4064(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd 4096(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x28,0xe6,0xaa,0x00,0x10,0x00,0x00]
|
||||
vcvtqq2pd 4096(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd -4096(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x28,0xe6,0x6a,0x80]
|
||||
vcvtqq2pd -4096(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd -4128(%rdx), %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x28,0xe6,0xaa,0xe0,0xef,0xff,0xff]
|
||||
vcvtqq2pd -4128(%rdx), %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd 1016(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x38,0xe6,0x6a,0x7f]
|
||||
vcvtqq2pd 1016(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd 1024(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x38,0xe6,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2pd 1024(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd -1024(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x38,0xe6,0x6a,0x80]
|
||||
vcvtqq2pd -1024(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2pd -1032(%rdx){1to4}, %ymm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x38,0xe6,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2pd -1032(%rdx){1to4}, %ymm21
|
||||
|
||||
// CHECK: vcvtqq2ps %xmm28, %xmm25
|
||||
// CHECK: encoding: [0x62,0x01,0xfc,0x08,0x5b,0xcc]
|
||||
vcvtqq2ps %xmm28, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps %xmm28, %xmm25 {%k6}
|
||||
// CHECK: encoding: [0x62,0x01,0xfc,0x0e,0x5b,0xcc]
|
||||
vcvtqq2ps %xmm28, %xmm25 {%k6}
|
||||
|
||||
// CHECK: vcvtqq2ps %xmm28, %xmm25 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0xfc,0x8e,0x5b,0xcc]
|
||||
vcvtqq2ps %xmm28, %xmm25 {%k6} {z}
|
||||
|
||||
// CHECK: vcvtqq2psx (%rcx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x08,0x5b,0x09]
|
||||
vcvtqq2psx (%rcx), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2psx 291(%rax,%r14,8), %xmm25
|
||||
// CHECK: encoding: [0x62,0x21,0xfc,0x08,0x5b,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2psx 291(%rax,%r14,8), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps (%rcx){1to2}, %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x18,0x5b,0x09]
|
||||
vcvtqq2ps (%rcx){1to2}, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2psx 2032(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x08,0x5b,0x4a,0x7f]
|
||||
vcvtqq2psx 2032(%rdx), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2psx 2048(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x08,0x5b,0x8a,0x00,0x08,0x00,0x00]
|
||||
vcvtqq2psx 2048(%rdx), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2psx -2048(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x08,0x5b,0x4a,0x80]
|
||||
vcvtqq2psx -2048(%rdx), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2psx -2064(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x08,0x5b,0x8a,0xf0,0xf7,0xff,0xff]
|
||||
vcvtqq2psx -2064(%rdx), %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps 1016(%rdx){1to2}, %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x18,0x5b,0x4a,0x7f]
|
||||
vcvtqq2ps 1016(%rdx){1to2}, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps 1024(%rdx){1to2}, %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x18,0x5b,0x8a,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2ps 1024(%rdx){1to2}, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps -1024(%rdx){1to2}, %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x18,0x5b,0x4a,0x80]
|
||||
vcvtqq2ps -1024(%rdx){1to2}, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps -1032(%rdx){1to2}, %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x18,0x5b,0x8a,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2ps -1032(%rdx){1to2}, %xmm25
|
||||
|
||||
// CHECK: vcvtqq2ps %ymm22, %xmm27
|
||||
// CHECK: encoding: [0x62,0x21,0xfc,0x28,0x5b,0xde]
|
||||
vcvtqq2ps %ymm22, %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps %ymm22, %xmm27 {%k3}
|
||||
// CHECK: encoding: [0x62,0x21,0xfc,0x2b,0x5b,0xde]
|
||||
vcvtqq2ps %ymm22, %xmm27 {%k3}
|
||||
|
||||
// CHECK: vcvtqq2ps %ymm22, %xmm27 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0xfc,0xab,0x5b,0xde]
|
||||
vcvtqq2ps %ymm22, %xmm27 {%k3} {z}
|
||||
|
||||
// CHECK: vcvtqq2psy (%rcx), %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x28,0x5b,0x19]
|
||||
vcvtqq2psy (%rcx), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2psy 291(%rax,%r14,8), %xmm27
|
||||
// CHECK: encoding: [0x62,0x21,0xfc,0x28,0x5b,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtqq2psy 291(%rax,%r14,8), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps (%rcx){1to4}, %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x38,0x5b,0x19]
|
||||
vcvtqq2ps (%rcx){1to4}, %xmm27
|
||||
|
||||
// CHECK: vcvtqq2psy 4064(%rdx), %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x28,0x5b,0x5a,0x7f]
|
||||
vcvtqq2psy 4064(%rdx), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2psy 4096(%rdx), %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x28,0x5b,0x9a,0x00,0x10,0x00,0x00]
|
||||
vcvtqq2psy 4096(%rdx), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2psy -4096(%rdx), %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x28,0x5b,0x5a,0x80]
|
||||
vcvtqq2psy -4096(%rdx), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2psy -4128(%rdx), %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x28,0x5b,0x9a,0xe0,0xef,0xff,0xff]
|
||||
vcvtqq2psy -4128(%rdx), %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps 1016(%rdx){1to4}, %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x38,0x5b,0x5a,0x7f]
|
||||
vcvtqq2ps 1016(%rdx){1to4}, %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps 1024(%rdx){1to4}, %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x38,0x5b,0x9a,0x00,0x04,0x00,0x00]
|
||||
vcvtqq2ps 1024(%rdx){1to4}, %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps -1024(%rdx){1to4}, %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x38,0x5b,0x5a,0x80]
|
||||
vcvtqq2ps -1024(%rdx){1to4}, %xmm27
|
||||
|
||||
// CHECK: vcvtqq2ps -1032(%rdx){1to4}, %xmm27
|
||||
// CHECK: encoding: [0x62,0x61,0xfc,0x38,0x5b,0x9a,0xf8,0xfb,0xff,0xff]
|
||||
vcvtqq2ps -1032(%rdx){1to4}, %xmm27
|
||||
|
||||
// CHECK: vcvtuqq2pd %xmm20, %xmm19
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x08,0x7a,0xdc]
|
||||
vcvtuqq2pd %xmm20, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd %xmm20, %xmm19 {%k3}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x0b,0x7a,0xdc]
|
||||
vcvtuqq2pd %xmm20, %xmm19 {%k3}
|
||||
|
||||
// CHECK: vcvtuqq2pd %xmm20, %xmm19 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x8b,0x7a,0xdc]
|
||||
vcvtuqq2pd %xmm20, %xmm19 {%k3} {z}
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0x7a,0x19]
|
||||
vcvtuqq2pd (%rcx), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd 291(%rax,%r14,8), %xmm19
|
||||
// CHECK: encoding: [0x62,0xa1,0xfe,0x08,0x7a,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtuqq2pd 291(%rax,%r14,8), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx){1to2}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0x7a,0x19]
|
||||
vcvtuqq2pd (%rcx){1to2}, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd 2032(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0x7a,0x5a,0x7f]
|
||||
vcvtuqq2pd 2032(%rdx), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd 2048(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0x7a,0x9a,0x00,0x08,0x00,0x00]
|
||||
vcvtuqq2pd 2048(%rdx), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd -2048(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0x7a,0x5a,0x80]
|
||||
vcvtuqq2pd -2048(%rdx), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd -2064(%rdx), %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x08,0x7a,0x9a,0xf0,0xf7,0xff,0xff]
|
||||
vcvtuqq2pd -2064(%rdx), %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd 1016(%rdx){1to2}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0x7a,0x5a,0x7f]
|
||||
vcvtuqq2pd 1016(%rdx){1to2}, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd 1024(%rdx){1to2}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0x7a,0x9a,0x00,0x04,0x00,0x00]
|
||||
vcvtuqq2pd 1024(%rdx){1to2}, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd -1024(%rdx){1to2}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0x7a,0x5a,0x80]
|
||||
vcvtuqq2pd -1024(%rdx){1to2}, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd -1032(%rdx){1to2}, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0xfe,0x18,0x7a,0x9a,0xf8,0xfb,0xff,0xff]
|
||||
vcvtuqq2pd -1032(%rdx){1to2}, %xmm19
|
||||
|
||||
// CHECK: vcvtuqq2pd %ymm26, %ymm28
|
||||
// CHECK: encoding: [0x62,0x01,0xfe,0x28,0x7a,0xe2]
|
||||
vcvtuqq2pd %ymm26, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd %ymm26, %ymm28 {%k4}
|
||||
// CHECK: encoding: [0x62,0x01,0xfe,0x2c,0x7a,0xe2]
|
||||
vcvtuqq2pd %ymm26, %ymm28 {%k4}
|
||||
|
||||
// CHECK: vcvtuqq2pd %ymm26, %ymm28 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0xfe,0xac,0x7a,0xe2]
|
||||
vcvtuqq2pd %ymm26, %ymm28 {%k4} {z}
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx), %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x28,0x7a,0x21]
|
||||
vcvtuqq2pd (%rcx), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd 291(%rax,%r14,8), %ymm28
|
||||
// CHECK: encoding: [0x62,0x21,0xfe,0x28,0x7a,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtuqq2pd 291(%rax,%r14,8), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd (%rcx){1to4}, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x38,0x7a,0x21]
|
||||
vcvtuqq2pd (%rcx){1to4}, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd 4064(%rdx), %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x28,0x7a,0x62,0x7f]
|
||||
vcvtuqq2pd 4064(%rdx), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd 4096(%rdx), %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x28,0x7a,0xa2,0x00,0x10,0x00,0x00]
|
||||
vcvtuqq2pd 4096(%rdx), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd -4096(%rdx), %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x28,0x7a,0x62,0x80]
|
||||
vcvtuqq2pd -4096(%rdx), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd -4128(%rdx), %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x28,0x7a,0xa2,0xe0,0xef,0xff,0xff]
|
||||
vcvtuqq2pd -4128(%rdx), %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd 1016(%rdx){1to4}, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x38,0x7a,0x62,0x7f]
|
||||
vcvtuqq2pd 1016(%rdx){1to4}, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd 1024(%rdx){1to4}, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x38,0x7a,0xa2,0x00,0x04,0x00,0x00]
|
||||
vcvtuqq2pd 1024(%rdx){1to4}, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd -1024(%rdx){1to4}, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x38,0x7a,0x62,0x80]
|
||||
vcvtuqq2pd -1024(%rdx){1to4}, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2pd -1032(%rdx){1to4}, %ymm28
|
||||
// CHECK: encoding: [0x62,0x61,0xfe,0x38,0x7a,0xa2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtuqq2pd -1032(%rdx){1to4}, %ymm28
|
||||
|
||||
// CHECK: vcvtuqq2ps %xmm27, %xmm21
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0x08,0x7a,0xeb]
|
||||
vcvtuqq2ps %xmm27, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps %xmm27, %xmm21 {%k7}
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0x0f,0x7a,0xeb]
|
||||
vcvtuqq2ps %xmm27, %xmm21 {%k7}
|
||||
|
||||
// CHECK: vcvtuqq2ps %xmm27, %xmm21 {%k7} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0xff,0x8f,0x7a,0xeb]
|
||||
vcvtuqq2ps %xmm27, %xmm21 {%k7} {z}
|
||||
|
||||
// CHECK: vcvtuqq2psx (%rcx), %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x29]
|
||||
vcvtuqq2psx (%rcx), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2psx 291(%rax,%r14,8), %xmm21
|
||||
// CHECK: encoding: [0x62,0xa1,0xff,0x08,0x7a,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtuqq2psx 291(%rax,%r14,8), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps (%rcx){1to2}, %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x18,0x7a,0x29]
|
||||
vcvtuqq2ps (%rcx){1to2}, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2psx 2032(%rdx), %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x6a,0x7f]
|
||||
vcvtuqq2psx 2032(%rdx), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2psx 2048(%rdx), %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0xaa,0x00,0x08,0x00,0x00]
|
||||
vcvtuqq2psx 2048(%rdx), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2psx -2048(%rdx), %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0x6a,0x80]
|
||||
vcvtuqq2psx -2048(%rdx), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2psx -2064(%rdx), %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x08,0x7a,0xaa,0xf0,0xf7,0xff,0xff]
|
||||
vcvtuqq2psx -2064(%rdx), %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps 1016(%rdx){1to2}, %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x18,0x7a,0x6a,0x7f]
|
||||
vcvtuqq2ps 1016(%rdx){1to2}, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps 1024(%rdx){1to2}, %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x18,0x7a,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtuqq2ps 1024(%rdx){1to2}, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps -1024(%rdx){1to2}, %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x18,0x7a,0x6a,0x80]
|
||||
vcvtuqq2ps -1024(%rdx){1to2}, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps -1032(%rdx){1to2}, %xmm21
|
||||
// CHECK: encoding: [0x62,0xe1,0xff,0x18,0x7a,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtuqq2ps -1032(%rdx){1to2}, %xmm21
|
||||
|
||||
// CHECK: vcvtuqq2ps %ymm24, %xmm28
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0x28,0x7a,0xe0]
|
||||
vcvtuqq2ps %ymm24, %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps %ymm24, %xmm28 {%k3}
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0x2b,0x7a,0xe0]
|
||||
vcvtuqq2ps %ymm24, %xmm28 {%k3}
|
||||
|
||||
// CHECK: vcvtuqq2ps %ymm24, %xmm28 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0xff,0xab,0x7a,0xe0]
|
||||
vcvtuqq2ps %ymm24, %xmm28 {%k3} {z}
|
||||
|
||||
// CHECK: vcvtuqq2psy (%rcx), %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7a,0x21]
|
||||
vcvtuqq2psy (%rcx), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2psy 291(%rax,%r14,8), %xmm28
|
||||
// CHECK: encoding: [0x62,0x21,0xff,0x28,0x7a,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtuqq2psy 291(%rax,%r14,8), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps (%rcx){1to4}, %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x38,0x7a,0x21]
|
||||
vcvtuqq2ps (%rcx){1to4}, %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2psy 4064(%rdx), %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7a,0x62,0x7f]
|
||||
vcvtuqq2psy 4064(%rdx), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2psy 4096(%rdx), %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7a,0xa2,0x00,0x10,0x00,0x00]
|
||||
vcvtuqq2psy 4096(%rdx), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2psy -4096(%rdx), %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7a,0x62,0x80]
|
||||
vcvtuqq2psy -4096(%rdx), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2psy -4128(%rdx), %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x28,0x7a,0xa2,0xe0,0xef,0xff,0xff]
|
||||
vcvtuqq2psy -4128(%rdx), %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps 1016(%rdx){1to4}, %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x38,0x7a,0x62,0x7f]
|
||||
vcvtuqq2ps 1016(%rdx){1to4}, %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps 1024(%rdx){1to4}, %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x38,0x7a,0xa2,0x00,0x04,0x00,0x00]
|
||||
vcvtuqq2ps 1024(%rdx){1to4}, %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps -1024(%rdx){1to4}, %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x38,0x7a,0x62,0x80]
|
||||
vcvtuqq2ps -1024(%rdx){1to4}, %xmm28
|
||||
|
||||
// CHECK: vcvtuqq2ps -1032(%rdx){1to4}, %xmm28
|
||||
// CHECK: encoding: [0x62,0x61,0xff,0x38,0x7a,0xa2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtuqq2ps -1032(%rdx){1to4}, %xmm28
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -243,6 +243,9 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_OPSIZE_KZ_B:
|
||||
return false;
|
||||
case IC_EVEX_W_K:
|
||||
case IC_EVEX_W_B:
|
||||
case IC_EVEX_W_K_B:
|
||||
case IC_EVEX_W_KZ_B:
|
||||
case IC_EVEX_W_XS_K:
|
||||
case IC_EVEX_W_XD_K:
|
||||
case IC_EVEX_W_OPSIZE_K:
|
||||
@ -252,6 +255,8 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_L_K:
|
||||
case IC_EVEX_L_XS_K:
|
||||
case IC_EVEX_L_XD_K:
|
||||
case IC_EVEX_L_XD_B:
|
||||
case IC_EVEX_L_XD_K_B:
|
||||
case IC_EVEX_L_OPSIZE_K:
|
||||
case IC_EVEX_L_OPSIZE_B:
|
||||
case IC_EVEX_L_OPSIZE_K_B:
|
||||
@ -272,21 +277,30 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_L_XS_KZ:
|
||||
case IC_EVEX_L_XS_B:
|
||||
case IC_EVEX_L_XS_K_B:
|
||||
case IC_EVEX_L_XS_KZ_B:
|
||||
case IC_EVEX_L_XD_KZ:
|
||||
case IC_EVEX_L_XD_KZ_B:
|
||||
case IC_EVEX_L_OPSIZE_KZ:
|
||||
case IC_EVEX_L_OPSIZE_KZ_B:
|
||||
return false;
|
||||
case IC_EVEX_L_W_K:
|
||||
case IC_EVEX_L_W_B:
|
||||
case IC_EVEX_L_W_K_B:
|
||||
case IC_EVEX_L_W_XS_K:
|
||||
case IC_EVEX_L_W_XS_B:
|
||||
case IC_EVEX_L_W_XS_K_B:
|
||||
case IC_EVEX_L_W_XD_K:
|
||||
case IC_EVEX_L_W_XS_KZ:
|
||||
case IC_EVEX_L_W_XS_KZ_B:
|
||||
case IC_EVEX_L_W_OPSIZE_K:
|
||||
case IC_EVEX_L_W_OPSIZE_B:
|
||||
case IC_EVEX_L_W_OPSIZE_K_B:
|
||||
case IC_EVEX_L_W_KZ:
|
||||
case IC_EVEX_L_W_XS_KZ:
|
||||
case IC_EVEX_L_W_KZ_B:
|
||||
case IC_EVEX_L_W_XD_K:
|
||||
case IC_EVEX_L_W_XD_B:
|
||||
case IC_EVEX_L_W_XD_K_B:
|
||||
case IC_EVEX_L_W_XD_KZ:
|
||||
case IC_EVEX_L_W_XD_KZ_B:
|
||||
case IC_EVEX_L_W_OPSIZE_KZ:
|
||||
case IC_EVEX_L_W_OPSIZE_KZ_B:
|
||||
return false;
|
||||
@ -299,17 +313,22 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_L2_XS_B:
|
||||
case IC_EVEX_L2_XD_B:
|
||||
case IC_EVEX_L2_XD_K:
|
||||
case IC_EVEX_L2_XD_K_B:
|
||||
case IC_EVEX_L2_OPSIZE_K:
|
||||
case IC_EVEX_L2_OPSIZE_B:
|
||||
case IC_EVEX_L2_OPSIZE_K_B:
|
||||
case IC_EVEX_L2_KZ:
|
||||
case IC_EVEX_L2_XS_KZ:
|
||||
case IC_EVEX_L2_XS_KZ_B:
|
||||
case IC_EVEX_L2_XD_KZ:
|
||||
case IC_EVEX_L2_XD_KZ_B:
|
||||
case IC_EVEX_L2_OPSIZE_KZ:
|
||||
case IC_EVEX_L2_OPSIZE_KZ_B:
|
||||
return false;
|
||||
case IC_EVEX_L2_W_K:
|
||||
case IC_EVEX_L2_W_B:
|
||||
case IC_EVEX_L2_W_K_B:
|
||||
case IC_EVEX_L2_W_KZ_B:
|
||||
case IC_EVEX_L2_W_XS_K:
|
||||
case IC_EVEX_L2_W_XS_B:
|
||||
case IC_EVEX_L2_W_XS_K_B:
|
||||
@ -320,7 +339,10 @@ static inline bool inheritsFrom(InstructionContext child,
|
||||
case IC_EVEX_L2_W_OPSIZE_K_B:
|
||||
case IC_EVEX_L2_W_KZ:
|
||||
case IC_EVEX_L2_W_XS_KZ:
|
||||
case IC_EVEX_L2_W_XS_KZ_B:
|
||||
case IC_EVEX_L2_W_XD_KZ:
|
||||
case IC_EVEX_L2_W_XD_K_B:
|
||||
case IC_EVEX_L2_W_XD_KZ_B:
|
||||
case IC_EVEX_L2_W_OPSIZE_KZ:
|
||||
case IC_EVEX_L2_W_OPSIZE_KZ_B:
|
||||
return false;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user