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synced 2024-12-04 18:06:49 +00:00
Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -854,8 +854,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VTRN: return "ARMISD::VTRN";
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case ARMISD::VTBL1: return "ARMISD::VTBL1";
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case ARMISD::VTBL2: return "ARMISD::VTBL2";
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case ARMISD::VTBL3: return "ARMISD::VTBL3";
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case ARMISD::VTBL4: return "ARMISD::VTBL4";
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case ARMISD::VMULLs: return "ARMISD::VMULLs";
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case ARMISD::VMULLu: return "ARMISD::VMULLu";
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case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
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@ -4076,10 +4074,10 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
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return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
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&VTBLMask[0], 8));
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else
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return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
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&VTBLMask[0], 8));
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return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
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&VTBLMask[0], 8));
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}
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static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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@ -155,8 +155,6 @@ namespace llvm {
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VTRN, // transpose
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VTBL1, // 1-register shuffle with mask
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VTBL2, // 2-register shuffle with mask
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VTBL3, // 3-register shuffle with mask
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VTBL4, // 4-register shuffle with mask
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// Vector multiply long:
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VMULLs, // ...signed
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@ -121,3 +121,15 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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ret <4 x i16> %tmp2
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}
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; The actual shuffle code only handles some cases, make sure we check
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; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
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; lowering loop can result otherwise).
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define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: test_illegal:
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;CHECK: vst1.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
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ret <8 x i16> %tmp3
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}
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