RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-22 20:18:38 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[InstCombine] allow shl demanded bits folds with splat constants

Browse Source 
More fixes are needed to enable the helper SimplifyShrShlDemandedBits().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300898 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2017-04-20 21:33:02 +00:00
parent 7b99ac1139
commit a24f137360
4 changed files with 9 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -469,8 +469,9 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
computeKnownBits(V, KnownZero, KnownOne, Depth, CxtI);
break;
}
case Instruction::Shl:
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
case Instruction::Shl: {
const APInt *SA;
if (match(I->getOperand(1), m_APInt(SA))) {
{
Value *VarX; ConstantInt *C1;
if (match(I->getOperand(0), m_Shr(m_Value(VarX), m_ConstantInt(C1)))) {
@ -503,6 +504,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
KnownZero.setLowBits(ShiftAmt);
}
break;
}
case Instruction::LShr: {
const APInt *SA;
if (match(I->getOperand(1), m_APInt(SA))) {

7
test/Transforms/InstCombine/apint-shift.ll
View File

@ -287,13 +287,10 @@ define i47 @test12(i47 %X) {
ret i47 %sh2
}
; FIXME: Same as above with vectors.
define <2 x i47> @test12_splat_vec(<2 x i47> %X) {
; CHECK-LABEL: @test12_splat_vec(
; CHECK-NEXT: [[SH1:%.*]] = ashr <2 x i47> %X, <i47 8, i47 8>
; CHECK-NEXT: [[SH2:%.*]] = shl nsw <2 x i47> [[SH1]], <i47 8, i47 8>
; CHECK-NEXT: ret <2 x i47> [[SH2]]
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i47> %X, <i47 -256, i47 -256>
; CHECK-NEXT: ret <2 x i47> [[TMP1]]
;
%sh1 = ashr <2 x i47> %X, <i47 8, i47 8>
%sh2 = shl <2 x i47> %sh1, <i47 8, i47 8>

4
test/Transforms/InstCombine/pr17827.ll
View File

@ -52,9 +52,7 @@ define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
; CHECK-LABEL: @test_shift_and_cmp_changed1_vec(
; CHECK-NEXT: [[ANDP:%.*]] = and <2 x i8> %p, <i8 6, i8 6>
; CHECK-NEXT: [[ANDQ:%.*]] = and <2 x i8> %q, <i8 8, i8 8>
; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[ANDQ]], [[ANDP]]
; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[OR]], <i8 5, i8 5>
; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i8> [[ANDP]], <i8 5, i8 5>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;

6
test/Transforms/InstCombine/shift.ll
View File

@ -1049,12 +1049,11 @@ define i8 @test53_no_nuw(i8 %x) {
}
; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2)
; FIXME: Demanded bits should change the mask constant as it does for the scalar case.
define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @test53_no_nuw_splat_vec(
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> %x, <i8 2, i8 2>
; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 127, i8 127>
; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124>
; CHECK-NEXT: ret <2 x i8> [[B]]
;
%A = shl <2 x i8> %x, <i8 3, i8 3>
@ -1257,8 +1256,7 @@ define i64 @test_64(i32 %t) {
define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
; CHECK-LABEL: @test_64_splat_vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %t, <i32 16777215, i32 16777215>
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw <2 x i32> [[AND]], <i32 8, i32 8>
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %t, <i32 8, i32 8>
; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[SHL]]
;