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[mips][ias] Fold needsExpansion() and expandInstruction() together. NFC.
Summary: Previously we maintained two separate switch statements that had to be kept in sync. This patch merges them into a single switch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14012 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251369 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
f94a25288b
commit
a2ab9668ec
@ -167,12 +167,16 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool parseOperand(OperandVector &, StringRef Mnemonic);
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bool needsExpansion(MCInst &Inst);
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enum MacroExpanderResultTy {
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MER_NotAMacro,
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MER_Success,
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MER_Fail,
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};
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// Expands assembly pseudo instructions.
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// Returns false on success, true otherwise.
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bool expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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MacroExpanderResultTy
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tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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@ -1601,8 +1605,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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}
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}
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// This expansion is not in a function called by expandInstruction() because
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// the pseudo-instruction doesn't have a distinct opcode.
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// This expansion is not in a function called by tryExpandInstruction()
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// because the pseudo-instruction doesn't have a distinct opcode.
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if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
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inPicMode()) {
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warnIfNoMacro(IDLoc);
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@ -1869,11 +1873,17 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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}
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}
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if (needsExpansion(Inst)) {
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if (expandInstruction(Inst, IDLoc, Instructions))
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return true;
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} else
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MacroExpanderResultTy ExpandResult =
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tryExpandInstruction(Inst, IDLoc, Instructions);
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switch (ExpandResult) {
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case MER_NotAMacro:
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Instructions.push_back(Inst);
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break;
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case MER_Success:
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break;
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case MER_Fail:
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return true;
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}
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// If this instruction has a delay slot and .set reorder is active,
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// emit a NOP after it.
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@ -1905,109 +1915,30 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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MipsAsmParser::MacroExpanderResultTy
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MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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switch (Inst.getOpcode()) {
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case Mips::LoadImm32:
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case Mips::LoadImm64:
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case Mips::LoadAddrImm32:
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case Mips::LoadAddrImm64:
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case Mips::LoadAddrReg32:
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case Mips::LoadAddrReg64:
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case Mips::B_MM_Pseudo:
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case Mips::B_MMR6_Pseudo:
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case Mips::LWM_MM:
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case Mips::SWM_MM:
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case Mips::JalOneReg:
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case Mips::JalTwoReg:
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case Mips::BneImm:
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case Mips::BeqImm:
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case Mips::BLT:
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case Mips::BLE:
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case Mips::BGE:
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case Mips::BGT:
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case Mips::BLTU:
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case Mips::BLEU:
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case Mips::BGEU:
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case Mips::BGTU:
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case Mips::BLTL:
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case Mips::BLEL:
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case Mips::BGEL:
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case Mips::BGTL:
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case Mips::BLTUL:
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case Mips::BLEUL:
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case Mips::BGEUL:
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case Mips::BGTUL:
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case Mips::BLTImmMacro:
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case Mips::BLEImmMacro:
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case Mips::BGEImmMacro:
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case Mips::BGTImmMacro:
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case Mips::BLTUImmMacro:
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case Mips::BLEUImmMacro:
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case Mips::BGEUImmMacro:
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case Mips::BGTUImmMacro:
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case Mips::BLTLImmMacro:
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case Mips::BLELImmMacro:
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case Mips::BGELImmMacro:
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case Mips::BGTLImmMacro:
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case Mips::BLTULImmMacro:
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case Mips::BLEULImmMacro:
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case Mips::BGEULImmMacro:
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case Mips::BGTULImmMacro:
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case Mips::SDivMacro:
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case Mips::UDivMacro:
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case Mips::DSDivMacro:
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case Mips::DUDivMacro:
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case Mips::Ulh:
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case Mips::Ulhu:
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case Mips::Ulw:
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case Mips::NORImm:
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return true;
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case Mips::ADDi:
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case Mips::ADDiu:
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case Mips::SLTi:
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case Mips::SLTiu:
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if ((Inst.getNumOperands() == 3) &&
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Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() &&
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Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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return !isInt<16>(ImmValue);
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}
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return false;
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case Mips::ANDi:
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case Mips::ORi:
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case Mips::XORi:
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if ((Inst.getNumOperands() == 3) &&
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Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() &&
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Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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return !isUInt<16>(ImmValue);
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}
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return false;
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default:
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return false;
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}
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}
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bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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switch (Inst.getOpcode()) {
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default: llvm_unreachable("unimplemented expansion");
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return MER_NotAMacro;
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case Mips::LoadImm32:
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return expandLoadImm(Inst, true, IDLoc, Instructions);
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return expandLoadImm(Inst, true, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::LoadImm64:
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return expandLoadImm(Inst, false, IDLoc, Instructions);
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return expandLoadImm(Inst, false, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::LoadAddrImm32:
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case Mips::LoadAddrImm64:
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assert(Inst.getOperand(0).isReg() && "expected register operand kind");
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assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) &&
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"expected immediate operand kind");
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return expandLoadAddress(
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Inst.getOperand(0).getReg(), Mips::NoRegister, Inst.getOperand(1),
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Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, Instructions);
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return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
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Inst.getOperand(1),
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Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
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Instructions)
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? MER_Fail
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: MER_Success;
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case Mips::LoadAddrReg32:
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case Mips::LoadAddrReg64:
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assert(Inst.getOperand(0).isReg() && "expected register operand kind");
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@ -2015,21 +1946,27 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) &&
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"expected immediate operand kind");
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return expandLoadAddress(
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Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(), Inst.getOperand(2),
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Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, Instructions);
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return expandLoadAddress(Inst.getOperand(0).getReg(),
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Inst.getOperand(1).getReg(), Inst.getOperand(2),
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Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
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Instructions)
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? MER_Fail
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: MER_Success;
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case Mips::B_MM_Pseudo:
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case Mips::B_MMR6_Pseudo:
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return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
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return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::SWM_MM:
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case Mips::LWM_MM:
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return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
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return expandLoadStoreMultiple(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::JalOneReg:
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case Mips::JalTwoReg:
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return expandJalWithRegs(Inst, IDLoc, Instructions);
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return expandJalWithRegs(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::BneImm:
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case Mips::BeqImm:
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return expandBranchImm(Inst, IDLoc, Instructions);
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return expandBranchImm(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success;
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case Mips::BLT:
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case Mips::BLE:
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case Mips::BGE:
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@ -2062,30 +1999,54 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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case Mips::BLEULImmMacro:
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case Mips::BGEULImmMacro:
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case Mips::BGTULImmMacro:
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return expandCondBranches(Inst, IDLoc, Instructions);
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return expandCondBranches(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::SDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, false, true);
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return expandDiv(Inst, IDLoc, Instructions, false, true) ? MER_Fail
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: MER_Success;
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case Mips::DSDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, true, true);
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return expandDiv(Inst, IDLoc, Instructions, true, true) ? MER_Fail
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: MER_Success;
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case Mips::UDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, false, false);
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return expandDiv(Inst, IDLoc, Instructions, false, false) ? MER_Fail
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: MER_Success;
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case Mips::DUDivMacro:
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return expandDiv(Inst, IDLoc, Instructions, true, false);
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return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail
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: MER_Success;
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case Mips::Ulh:
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return expandUlh(Inst, true, IDLoc, Instructions);
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return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success;
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case Mips::Ulhu:
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return expandUlh(Inst, false, IDLoc, Instructions);
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return expandUlh(Inst, false, IDLoc, Instructions) ? MER_Fail : MER_Success;
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case Mips::Ulw:
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return expandUlw(Inst, IDLoc, Instructions);
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return expandUlw(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success;
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case Mips::NORImm:
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return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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case Mips::ADDi:
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case Mips::ADDiu:
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case Mips::ANDi:
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case Mips::NORImm:
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case Mips::ORi:
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case Mips::SLTi:
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case Mips::SLTiu:
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if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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if (isInt<16>(ImmValue))
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return MER_NotAMacro;
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return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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}
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return MER_NotAMacro;
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case Mips::ANDi:
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case Mips::ORi:
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case Mips::XORi:
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return expandAliasImmediate(Inst, IDLoc, Instructions);
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if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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if (isUInt<16>(ImmValue))
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return MER_NotAMacro;
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return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail
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: MER_Success;
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}
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return MER_NotAMacro;
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}
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}
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