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https://github.com/RPCSX/llvm.git
synced 2024-11-29 14:40:25 +00:00
Turn the Edit member into a pointer so it can change dynamically.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126898 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -216,13 +216,13 @@ SplitEditor::SplitEditor(SplitAnalysis &sa,
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MDT(mdt),
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TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
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TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
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Edit(edit),
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Edit(&edit),
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OpenIdx(0),
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RegAssign(Allocator)
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{
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// We don't need an AliasAnalysis since we will only be performing
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// cheap-as-a-copy remats anyway.
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Edit.anyRematerializable(LIS, TII, 0);
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Edit->anyRematerializable(LIS, TII, 0);
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}
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void SplitEditor::dump() const {
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@ -241,8 +241,8 @@ VNInfo *SplitEditor::defValue(unsigned RegIdx,
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SlotIndex Idx) {
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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assert(Edit.getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
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LiveInterval *LI = Edit.get(RegIdx);
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assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
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LiveInterval *LI = Edit->get(RegIdx);
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// Create a new value.
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VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
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@ -286,7 +286,7 @@ void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
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// This was previously a single mapping. Make sure the old def is represented
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// by a trivial live range.
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SlotIndex Def = VNI->def;
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Edit.get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
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Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
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VNI = 0;
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}
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@ -296,7 +296,7 @@ void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
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assert(Idx.isValid() && "Invalid SlotIndex");
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MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
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assert(IdxMBB && "No MBB at Idx");
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LiveInterval *LI = Edit.get(RegIdx);
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LiveInterval *LI = Edit->get(RegIdx);
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// Is there a def in the same MBB we can extend?
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if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
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@ -384,7 +384,7 @@ VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
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const MachineBasicBlock *IdxMBB) {
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// This is essentially the same iterative algorithm that SSAUpdater uses,
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// except we already have a dominator tree, so we don't have to recompute it.
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LiveInterval *LI = Edit.get(RegIdx);
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LiveInterval *LI = Edit->get(RegIdx);
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VNInfo *IdxVNI = 0;
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unsigned Changes;
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do {
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@ -488,16 +488,16 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
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MachineBasicBlock::iterator I) {
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MachineInstr *CopyMI = 0;
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SlotIndex Def;
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LiveInterval *LI = Edit.get(RegIdx);
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LiveInterval *LI = Edit->get(RegIdx);
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// Attempt cheap-as-a-copy rematerialization.
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LiveRangeEdit::Remat RM(ParentVNI);
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if (Edit.canRematerializeAt(RM, UseIdx, true, LIS)) {
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Def = Edit.rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
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if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
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Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
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} else {
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// Can't remat, just insert a copy from parent.
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CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
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.addReg(Edit.getReg());
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.addReg(Edit->getReg());
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Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
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}
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@ -512,19 +512,19 @@ void SplitEditor::openIntv() {
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assert(!OpenIdx && "Previous LI not closed before openIntv");
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// Create the complement as index 0.
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if (Edit.empty())
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Edit.create(MRI, LIS, VRM);
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if (Edit->empty())
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Edit->create(MRI, LIS, VRM);
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// Create the open interval.
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OpenIdx = Edit.size();
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Edit.create(MRI, LIS, VRM);
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OpenIdx = Edit->size();
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Edit->create(MRI, LIS, VRM);
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}
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SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
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assert(OpenIdx && "openIntv not called before enterIntvBefore");
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DEBUG(dbgs() << " enterIntvBefore " << Idx);
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Idx = Idx.getBaseIndex();
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VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
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if (!ParentVNI) {
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DEBUG(dbgs() << ": not live\n");
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return Idx;
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@ -542,14 +542,14 @@ SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
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SlotIndex End = LIS.getMBBEndIdx(&MBB);
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SlotIndex Last = End.getPrevSlot();
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DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
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VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Last);
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
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if (!ParentVNI) {
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DEBUG(dbgs() << ": not live\n");
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return End;
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}
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DEBUG(dbgs() << ": valno " << ParentVNI->id);
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VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
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LIS.getLastSplitPoint(Edit.getParent(), &MBB));
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LIS.getLastSplitPoint(Edit->getParent(), &MBB));
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RegAssign.insert(VNI->def, End, OpenIdx);
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DEBUG(dump());
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return VNI->def;
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@ -573,7 +573,7 @@ SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
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// The interval must be live beyond the instruction at Idx.
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Idx = Idx.getBoundaryIndex();
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VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
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if (!ParentVNI) {
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DEBUG(dbgs() << ": not live\n");
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return Idx.getNextSlot();
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@ -593,7 +593,7 @@ SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
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// The interval must be live into the instruction at Idx.
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Idx = Idx.getBoundaryIndex();
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VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
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if (!ParentVNI) {
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DEBUG(dbgs() << ": not live\n");
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return Idx.getNextSlot();
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@ -611,7 +611,7 @@ SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
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SlotIndex Start = LIS.getMBBStartIdx(&MBB);
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DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
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VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Start);
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VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
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if (!ParentVNI) {
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DEBUG(dbgs() << ": not live\n");
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return Start;
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@ -626,8 +626,8 @@ SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
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void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
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assert(OpenIdx && "openIntv not called before overlapIntv");
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const VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Start);
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assert(ParentVNI == Edit.getParent().getVNInfoAt(End.getPrevSlot()) &&
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const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
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assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
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"Parent changes value in extended range");
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assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
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"Range cannot span basic blocks");
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@ -652,8 +652,8 @@ void SplitEditor::closeIntv() {
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bool SplitEditor::transferSimpleValues() {
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bool Skipped = false;
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RegAssignMap::const_iterator AssignI = RegAssign.begin();
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for (LiveInterval::const_iterator ParentI = Edit.getParent().begin(),
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ParentE = Edit.getParent().end(); ParentI != ParentE; ++ParentI) {
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for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
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ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
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DEBUG(dbgs() << " blit " << *ParentI << ':');
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VNInfo *ParentVNI = ParentI->valno;
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// RegAssign has holes where RegIdx 0 should be used.
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@ -677,7 +677,7 @@ bool SplitEditor::transferSimpleValues() {
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DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
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if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
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DEBUG(dbgs() << ':' << VNI->id);
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Edit.get(RegIdx)->addRange(LiveRange(Start, End, VNI));
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Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
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} else
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Skipped = true;
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Start = End;
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@ -689,8 +689,8 @@ bool SplitEditor::transferSimpleValues() {
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void SplitEditor::extendPHIKillRanges() {
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// Extend live ranges to be live-out for successor PHI values.
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for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
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E = Edit.getParent().vni_end(); I != E; ++I) {
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for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
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E = Edit->getParent().vni_end(); I != E; ++I) {
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const VNInfo *PHIVNI = *I;
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if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
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continue;
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@ -701,7 +701,7 @@ void SplitEditor::extendPHIKillRanges() {
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SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
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// The predecessor may not have a live-out value. That is OK, like an
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// undef PHI operand.
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if (Edit.getParent().liveAt(End)) {
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if (Edit->getParent().liveAt(End)) {
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assert(RegAssign.lookup(End) == RegIdx &&
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"Different register assignment in phi predecessor");
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extendRange(RegIdx, End);
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@ -710,9 +710,9 @@ void SplitEditor::extendPHIKillRanges() {
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}
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}
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/// rewriteAssigned - Rewrite all uses of Edit.getReg().
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/// rewriteAssigned - Rewrite all uses of Edit->getReg().
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void SplitEditor::rewriteAssigned(bool ExtendRanges) {
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for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit.getReg()),
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for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
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RE = MRI.reg_end(); RI != RE;) {
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MachineOperand &MO = RI.getOperand();
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MachineInstr *MI = MO.getParent();
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@ -727,7 +727,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
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// <undef> operands don't really read the register, so just assign them to
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// the complement.
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if (MO.isUse() && MO.isUndef()) {
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MO.setReg(Edit.get(0)->reg);
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MO.setReg(Edit->get(0)->reg);
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continue;
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}
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@ -736,7 +736,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
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// Rewrite to the mapped register at Idx.
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unsigned RegIdx = RegAssign.lookup(Idx);
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MO.setReg(Edit.get(RegIdx)->reg);
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MO.setReg(Edit->get(RegIdx)->reg);
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DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
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<< Idx << ':' << RegIdx << '\t' << *MI);
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@ -776,8 +776,8 @@ void SplitEditor::finish() {
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// the inserted copies.
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// Add the original defs from the parent interval.
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for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
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E = Edit.getParent().vni_end(); I != E; ++I) {
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for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
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E = Edit->getParent().vni_end(); I != E; ++I) {
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const VNInfo *ParentVNI = *I;
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if (ParentVNI->isUnused())
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continue;
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@ -785,14 +785,14 @@ void SplitEditor::finish() {
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defValue(RegIdx, ParentVNI, ParentVNI->def);
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// Mark rematted values as complex everywhere to force liveness computation.
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// The new live ranges may be truncated.
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if (Edit.didRematerialize(ParentVNI))
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for (unsigned i = 0, e = Edit.size(); i != e; ++i)
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if (Edit->didRematerialize(ParentVNI))
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for (unsigned i = 0, e = Edit->size(); i != e; ++i)
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markComplexMapped(i, ParentVNI);
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}
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#ifndef NDEBUG
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// Every new interval must have a def by now, otherwise the split is bogus.
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for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
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for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
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assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
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#endif
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@ -809,14 +809,14 @@ void SplitEditor::finish() {
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// FIXME: Delete defs that were rematted everywhere.
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// Get rid of unused values and set phi-kill flags.
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for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
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for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
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(*I)->RenumberValues(LIS);
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// Now check if any registers were separated into multiple components.
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ConnectedVNInfoEqClasses ConEQ(LIS);
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for (unsigned i = 0, e = Edit.size(); i != e; ++i) {
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for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
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// Don't use iterators, they are invalidated by create() below.
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LiveInterval *li = Edit.get(i);
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LiveInterval *li = Edit->get(i);
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unsigned NumComp = ConEQ.Classify(li);
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if (NumComp <= 1)
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continue;
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@ -824,14 +824,14 @@ void SplitEditor::finish() {
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SmallVector<LiveInterval*, 8> dups;
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dups.push_back(li);
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for (unsigned i = 1; i != NumComp; ++i)
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dups.push_back(&Edit.create(MRI, LIS, VRM));
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dups.push_back(&Edit->create(MRI, LIS, VRM));
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rewriteComponents(dups, ConEQ);
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ConEQ.Distribute(&dups[0]);
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}
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// Calculate spill weight and allocation hints for new intervals.
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VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
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for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I){
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for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
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LiveInterval &li = **I;
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vrai.CalculateRegClass(li.reg);
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vrai.CalculateWeightAndHint(li);
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@ -165,7 +165,7 @@ class SplitEditor {
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const TargetRegisterInfo &TRI;
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/// Edit - The current parent register and new intervals created.
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LiveRangeEdit &Edit;
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LiveRangeEdit *Edit;
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/// Index into Edit of the currently open interval.
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/// The index 0 is used for the complement, so the first interval started by
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