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Extract method ProcessUses from LocalRewriter::RewriteMBB. Both parent and child
are still way too long, but it's a start. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
657985eb8b
commit
a32181a57d
@ -1110,6 +1110,12 @@ private:
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bool InsertSpills(MachineInstr *MI);
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void ProcessUses(MachineInstr &MI, AvailableSpills &Spills,
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std::vector<MachineInstr*> &MaybeDeadStores,
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BitVector &RegKills,
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ReuseInfo &ReusedOperands,
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std::vector<MachineOperand*> &KillOps);
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void RewriteMBB(LiveIntervals *LIs,
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AvailableSpills &Spills, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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@ -1828,7 +1834,7 @@ bool LocalRewriter::InsertRestores(MachineInstr *MI,
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return true;
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}
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/// InsertEmergencySpills - Insert spills after MI if requested by VRM. Return
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/// InsertSpills - Insert spills after MI if requested by VRM. Return
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/// true if spills were inserted.
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bool LocalRewriter::InsertSpills(MachineInstr *MI) {
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if (!VRM->isSpillPt(MI))
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@ -1856,6 +1862,334 @@ bool LocalRewriter::InsertSpills(MachineInstr *MI) {
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}
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/// ProcessUses - Process all of MI's spilled operands and all available
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/// operands.
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void LocalRewriter::ProcessUses(MachineInstr &MI, AvailableSpills &Spills,
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std::vector<MachineInstr*> &MaybeDeadStores,
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BitVector &RegKills,
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ReuseInfo &ReusedOperands,
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std::vector<MachineOperand*> &KillOps) {
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// Clear kill info.
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SmallSet<unsigned, 2> KilledMIRegs;
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SmallVector<unsigned, 4> VirtUseOps;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.getReg() == 0)
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continue; // Ignore non-register operands.
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unsigned VirtReg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
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// Ignore physregs for spilling, but remember that it is used by this
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// function.
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MRI->setPhysRegUsed(VirtReg);
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continue;
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}
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// We want to process implicit virtual register uses first.
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if (MO.isImplicit())
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// If the virtual register is implicitly defined, emit a implicit_def
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// before so scavenger knows it's "defined".
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// FIXME: This is a horrible hack done the by register allocator to
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// remat a definition with virtual register operand.
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VirtUseOps.insert(VirtUseOps.begin(), i);
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else
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VirtUseOps.push_back(i);
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}
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// Process all of the spilled uses and all non spilled reg references.
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SmallVector<int, 2> PotentialDeadStoreSlots;
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KilledMIRegs.clear();
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for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
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unsigned i = VirtUseOps[j];
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unsigned VirtReg = MI.getOperand(i).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Not a virtual register?");
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unsigned SubIdx = MI.getOperand(i).getSubReg();
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if (VRM->isAssignedReg(VirtReg)) {
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// This virtual register was assigned a physreg!
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unsigned Phys = VRM->getPhys(VirtReg);
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MRI->setPhysRegUsed(Phys);
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if (MI.getOperand(i).isDef())
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ReusedOperands.markClobbered(Phys);
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substitutePhysReg(MI.getOperand(i), Phys, *TRI);
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if (VRM->isImplicitlyDefined(VirtReg))
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// FIXME: Is this needed?
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BuildMI(*MBB, &MI, MI.getDebugLoc(),
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TII->get(TargetOpcode::IMPLICIT_DEF), Phys);
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continue;
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}
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// This virtual register is now known to be a spilled value.
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if (!MI.getOperand(i).isUse())
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continue; // Handle defs in the loop below (handle use&def here though)
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bool AvoidReload = MI.getOperand(i).isUndef();
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// Check if it is defined by an implicit def. It should not be spilled.
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// Note, this is for correctness reason. e.g.
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// 8 %reg1024<def> = IMPLICIT_DEF
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// 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
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// The live range [12, 14) are not part of the r1024 live interval since
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// it's defined by an implicit def. It will not conflicts with live
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// interval of r1025. Now suppose both registers are spilled, you can
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// easily see a situation where both registers are reloaded before
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// the INSERT_SUBREG and both target registers that would overlap.
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bool DoReMat = VRM->isReMaterialized(VirtReg);
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int SSorRMId = DoReMat
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? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
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int ReuseSlot = SSorRMId;
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// Check to see if this stack slot is available.
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unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
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// If this is a sub-register use, make sure the reuse register is in the
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// right register class. For example, for x86 not all of the 32-bit
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// registers have accessible sub-registers.
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// Similarly so for EXTRACT_SUBREG. Consider this:
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// EDI = op
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// MOV32_mr fi#1, EDI
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// ...
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// = EXTRACT_SUBREG fi#1
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// fi#1 is available in EDI, but it cannot be reused because it's not in
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// the right register file.
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if (PhysReg && !AvoidReload && SubIdx) {
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const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
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if (!RC->contains(PhysReg))
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PhysReg = 0;
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}
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if (PhysReg && !AvoidReload) {
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// This spilled operand might be part of a two-address operand. If this
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// is the case, then changing it will necessarily require changing the
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// def part of the instruction as well. However, in some cases, we
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// aren't allowed to modify the reused register. If none of these cases
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// apply, reuse it.
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bool CanReuse = true;
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bool isTied = MI.isRegTiedToDefOperand(i);
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if (isTied) {
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// Okay, we have a two address operand. We can reuse this physreg as
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// long as we are allowed to clobber the value and there isn't an
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// earlier def that has already clobbered the physreg.
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CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
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Spills.canClobberPhysReg(PhysReg);
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}
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// If this is an asm, and a PhysReg alias is used elsewhere as an
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// earlyclobber operand, we can't also use it as an input.
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if (MI.isInlineAsm()) {
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for (unsigned k = 0, e = MI.getNumOperands(); k != e; ++k) {
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MachineOperand &MOk = MI.getOperand(k);
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if (MOk.isReg() && MOk.isEarlyClobber() &&
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TRI->regsOverlap(MOk.getReg(), PhysReg)) {
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CanReuse = false;
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DEBUG(dbgs() << "Not reusing physreg " << TRI->getName(PhysReg)
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<< " for vreg" << VirtReg << ": " << MOk << '\n');
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break;
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}
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}
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}
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if (CanReuse) {
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// If this stack slot value is already available, reuse it!
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if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
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DEBUG(dbgs() << "Reusing RM#"
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<< ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
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else
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DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
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DEBUG(dbgs() << " from physreg "
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<< TRI->getName(PhysReg) << " for vreg"
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<< VirtReg <<" instead of reloading into physreg "
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<< TRI->getName(VRM->getPhys(VirtReg)) << '\n');
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unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
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MI.getOperand(i).setReg(RReg);
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MI.getOperand(i).setSubReg(0);
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// The only technical detail we have is that we don't know that
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// PhysReg won't be clobbered by a reloaded stack slot that occurs
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// later in the instruction. In particular, consider 'op V1, V2'.
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// If V1 is available in physreg R0, we would choose to reuse it
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// here, instead of reloading it into the register the allocator
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// indicated (say R1). However, V2 might have to be reloaded
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// later, and it might indicate that it needs to live in R0. When
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// this occurs, we need to have information available that
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// indicates it is safe to use R1 for the reload instead of R0.
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//
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// To further complicate matters, we might conflict with an alias,
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// or R0 and R1 might not be compatible with each other. In this
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// case, we actually insert a reload for V1 in R1, ensuring that
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// we can get at R0 or its alias.
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ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
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VRM->getPhys(VirtReg), VirtReg);
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if (isTied)
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// Only mark it clobbered if this is a use&def operand.
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ReusedOperands.markClobbered(PhysReg);
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++NumReused;
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if (MI.getOperand(i).isKill() &&
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ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
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// The store of this spilled value is potentially dead, but we
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// won't know for certain until we've confirmed that the re-use
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// above is valid, which means waiting until the other operands
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// are processed. For now we just track the spill slot, we'll
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// remove it after the other operands are processed if valid.
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PotentialDeadStoreSlots.push_back(ReuseSlot);
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}
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// Mark is isKill if it's there no other uses of the same virtual
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// register and it's not a two-address operand. IsKill will be
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// unset if reg is reused.
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if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
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MI.getOperand(i).setIsKill();
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KilledMIRegs.insert(VirtReg);
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}
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continue;
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} // CanReuse
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// Otherwise we have a situation where we have a two-address instruction
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// whose mod/ref operand needs to be reloaded. This reload is already
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// available in some register "PhysReg", but if we used PhysReg as the
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// operand to our 2-addr instruction, the instruction would modify
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// PhysReg. This isn't cool if something later uses PhysReg and expects
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// to get its initial value.
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//
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// To avoid this problem, and to avoid doing a load right after a store,
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// we emit a copy from PhysReg into the designated register for this
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// operand.
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//
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// This case also applies to an earlyclobber'd PhysReg.
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unsigned DesignatedReg = VRM->getPhys(VirtReg);
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assert(DesignatedReg && "Must map virtreg to physreg!");
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// Note that, if we reused a register for a previous operand, the
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// register we want to reload into might not actually be
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// available. If this occurs, use the register indicated by the
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// reuser.
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if (ReusedOperands.hasReuses())
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DesignatedReg = ReusedOperands.
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GetRegForReload(VirtReg, DesignatedReg, &MI, Spills,
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MaybeDeadStores, RegKills, KillOps, *VRM);
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// If the mapped designated register is actually the physreg we have
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// incoming, we don't need to inserted a dead copy.
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if (DesignatedReg == PhysReg) {
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// If this stack slot value is already available, reuse it!
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if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
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DEBUG(dbgs() << "Reusing RM#"
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<< ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
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else
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DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
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DEBUG(dbgs() << " from physreg " << TRI->getName(PhysReg)
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<< " for vreg" << VirtReg
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<< " instead of reloading into same physreg.\n");
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unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
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MI.getOperand(i).setReg(RReg);
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MI.getOperand(i).setSubReg(0);
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ReusedOperands.markClobbered(RReg);
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++NumReused;
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continue;
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}
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MRI->setPhysRegUsed(DesignatedReg);
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ReusedOperands.markClobbered(DesignatedReg);
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// Back-schedule reloads and remats.
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MachineBasicBlock::iterator InsertLoc =
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ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
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SSorRMId, TII, *MBB->getParent());
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MachineInstr *CopyMI = BuildMI(*MBB, InsertLoc, MI.getDebugLoc(),
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TII->get(TargetOpcode::COPY),
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DesignatedReg).addReg(PhysReg);
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CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
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UpdateKills(*CopyMI, TRI, RegKills, KillOps);
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// This invalidates DesignatedReg.
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Spills.ClobberPhysReg(DesignatedReg);
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Spills.addAvailable(ReuseSlot, DesignatedReg);
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unsigned RReg =
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SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
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MI.getOperand(i).setReg(RReg);
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MI.getOperand(i).setSubReg(0);
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DEBUG(dbgs() << '\t' << *prior(InsertLoc));
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++NumReused;
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continue;
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} // if (PhysReg)
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// Otherwise, reload it and remember that we have it.
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PhysReg = VRM->getPhys(VirtReg);
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assert(PhysReg && "Must map virtreg to physreg!");
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// Note that, if we reused a register for a previous operand, the
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// register we want to reload into might not actually be
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// available. If this occurs, use the register indicated by the
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// reuser.
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if (ReusedOperands.hasReuses())
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PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
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Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
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MRI->setPhysRegUsed(PhysReg);
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ReusedOperands.markClobbered(PhysReg);
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if (AvoidReload)
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++NumAvoided;
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else {
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// Back-schedule reloads and remats.
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MachineBasicBlock::iterator InsertLoc =
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ComputeReloadLoc(MI, MBB->begin(), PhysReg, TRI, DoReMat,
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SSorRMId, TII, *MBB->getParent());
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if (DoReMat) {
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ReMaterialize(*MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, *VRM);
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} else {
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const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
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TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC,TRI);
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MachineInstr *LoadMI = prior(InsertLoc);
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VRM->addSpillSlotUse(SSorRMId, LoadMI);
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++NumLoads;
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DistanceMap.insert(std::make_pair(LoadMI, DistanceMap.size()));
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}
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// This invalidates PhysReg.
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Spills.ClobberPhysReg(PhysReg);
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// Any stores to this stack slot are not dead anymore.
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if (!DoReMat)
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MaybeDeadStores[SSorRMId] = NULL;
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Spills.addAvailable(SSorRMId, PhysReg);
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// Assumes this is the last use. IsKill will be unset if reg is reused
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// unless it's a two-address operand.
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if (!MI.isRegTiedToDefOperand(i) &&
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KilledMIRegs.count(VirtReg) == 0) {
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MI.getOperand(i).setIsKill();
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KilledMIRegs.insert(VirtReg);
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}
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UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
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DEBUG(dbgs() << '\t' << *prior(InsertLoc));
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}
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unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
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MI.getOperand(i).setReg(RReg);
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MI.getOperand(i).setSubReg(0);
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}
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// Ok - now we can remove stores that have been confirmed dead.
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for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
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// This was the last use and the spilled value is still available
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// for reuse. That means the spill was unnecessary!
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int PDSSlot = PotentialDeadStoreSlots[j];
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MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
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if (DeadStore) {
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DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
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InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
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VRM->RemoveMachineInstrFromMaps(DeadStore);
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MBB->erase(DeadStore);
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MaybeDeadStores[PDSSlot] = NULL;
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++NumDSE;
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}
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}
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}
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/// rewriteMBB - Keep track of which spills are available even after the
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/// register allocator is done with them. If possible, avoid reloading vregs.
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void
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@ -1880,9 +2214,6 @@ LocalRewriter::RewriteMBB(LiveIntervals *LIs,
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// ReMatDefs - These are rematerializable def MIs which are not deleted.
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SmallSet<MachineInstr*, 4> ReMatDefs;
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// Clear kill info.
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SmallSet<unsigned, 2> KilledMIRegs;
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// Keep track of the registers we have already spilled in case there are
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// multiple defs of the same register in MI.
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SmallSet<unsigned, 8> SpilledMIRegs;
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@ -1918,323 +2249,8 @@ LocalRewriter::RewriteMBB(LiveIntervals *LIs,
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/// ReusedOperands - Keep track of operand reuse in case we need to undo
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/// reuse.
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ReuseInfo ReusedOperands(MI, TRI);
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SmallVector<unsigned, 4> VirtUseOps;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || MO.getReg() == 0)
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continue; // Ignore non-register operands.
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unsigned VirtReg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
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// Ignore physregs for spilling, but remember that it is used by this
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// function.
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MRI->setPhysRegUsed(VirtReg);
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continue;
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}
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// We want to process implicit virtual register uses first.
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if (MO.isImplicit())
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// If the virtual register is implicitly defined, emit a implicit_def
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// before so scavenger knows it's "defined".
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// FIXME: This is a horrible hack done the by register allocator to
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// remat a definition with virtual register operand.
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VirtUseOps.insert(VirtUseOps.begin(), i);
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else
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VirtUseOps.push_back(i);
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}
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// Process all of the spilled uses and all non spilled reg references.
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SmallVector<int, 2> PotentialDeadStoreSlots;
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KilledMIRegs.clear();
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for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
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unsigned i = VirtUseOps[j];
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unsigned VirtReg = MI.getOperand(i).getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
||||
"Not a virtual register?");
|
||||
|
||||
unsigned SubIdx = MI.getOperand(i).getSubReg();
|
||||
if (VRM->isAssignedReg(VirtReg)) {
|
||||
// This virtual register was assigned a physreg!
|
||||
unsigned Phys = VRM->getPhys(VirtReg);
|
||||
MRI->setPhysRegUsed(Phys);
|
||||
if (MI.getOperand(i).isDef())
|
||||
ReusedOperands.markClobbered(Phys);
|
||||
substitutePhysReg(MI.getOperand(i), Phys, *TRI);
|
||||
if (VRM->isImplicitlyDefined(VirtReg))
|
||||
// FIXME: Is this needed?
|
||||
BuildMI(*MBB, &MI, MI.getDebugLoc(),
|
||||
TII->get(TargetOpcode::IMPLICIT_DEF), Phys);
|
||||
continue;
|
||||
}
|
||||
|
||||
// This virtual register is now known to be a spilled value.
|
||||
if (!MI.getOperand(i).isUse())
|
||||
continue; // Handle defs in the loop below (handle use&def here though)
|
||||
|
||||
bool AvoidReload = MI.getOperand(i).isUndef();
|
||||
// Check if it is defined by an implicit def. It should not be spilled.
|
||||
// Note, this is for correctness reason. e.g.
|
||||
// 8 %reg1024<def> = IMPLICIT_DEF
|
||||
// 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
|
||||
// The live range [12, 14) are not part of the r1024 live interval since
|
||||
// it's defined by an implicit def. It will not conflicts with live
|
||||
// interval of r1025. Now suppose both registers are spilled, you can
|
||||
// easily see a situation where both registers are reloaded before
|
||||
// the INSERT_SUBREG and both target registers that would overlap.
|
||||
bool DoReMat = VRM->isReMaterialized(VirtReg);
|
||||
int SSorRMId = DoReMat
|
||||
? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
|
||||
int ReuseSlot = SSorRMId;
|
||||
|
||||
// Check to see if this stack slot is available.
|
||||
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
|
||||
|
||||
// If this is a sub-register use, make sure the reuse register is in the
|
||||
// right register class. For example, for x86 not all of the 32-bit
|
||||
// registers have accessible sub-registers.
|
||||
// Similarly so for EXTRACT_SUBREG. Consider this:
|
||||
// EDI = op
|
||||
// MOV32_mr fi#1, EDI
|
||||
// ...
|
||||
// = EXTRACT_SUBREG fi#1
|
||||
// fi#1 is available in EDI, but it cannot be reused because it's not in
|
||||
// the right register file.
|
||||
if (PhysReg && !AvoidReload && SubIdx) {
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
if (!RC->contains(PhysReg))
|
||||
PhysReg = 0;
|
||||
}
|
||||
|
||||
if (PhysReg && !AvoidReload) {
|
||||
// This spilled operand might be part of a two-address operand. If this
|
||||
// is the case, then changing it will necessarily require changing the
|
||||
// def part of the instruction as well. However, in some cases, we
|
||||
// aren't allowed to modify the reused register. If none of these cases
|
||||
// apply, reuse it.
|
||||
bool CanReuse = true;
|
||||
bool isTied = MI.isRegTiedToDefOperand(i);
|
||||
if (isTied) {
|
||||
// Okay, we have a two address operand. We can reuse this physreg as
|
||||
// long as we are allowed to clobber the value and there isn't an
|
||||
// earlier def that has already clobbered the physreg.
|
||||
CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
|
||||
Spills.canClobberPhysReg(PhysReg);
|
||||
}
|
||||
// If this is an asm, and a PhysReg alias is used elsewhere as an
|
||||
// earlyclobber operand, we can't also use it as an input.
|
||||
if (MI.isInlineAsm()) {
|
||||
for (unsigned k = 0, e = MI.getNumOperands(); k != e; ++k) {
|
||||
MachineOperand &MOk = MI.getOperand(k);
|
||||
if (MOk.isReg() && MOk.isEarlyClobber() &&
|
||||
TRI->regsOverlap(MOk.getReg(), PhysReg)) {
|
||||
CanReuse = false;
|
||||
DEBUG(dbgs() << "Not reusing physreg " << TRI->getName(PhysReg)
|
||||
<< " for vreg" << VirtReg << ": " << MOk << '\n');
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (CanReuse) {
|
||||
// If this stack slot value is already available, reuse it!
|
||||
if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
|
||||
DEBUG(dbgs() << "Reusing RM#"
|
||||
<< ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
|
||||
else
|
||||
DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
|
||||
DEBUG(dbgs() << " from physreg "
|
||||
<< TRI->getName(PhysReg) << " for vreg"
|
||||
<< VirtReg <<" instead of reloading into physreg "
|
||||
<< TRI->getName(VRM->getPhys(VirtReg)) << '\n');
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
MI.getOperand(i).setSubReg(0);
|
||||
|
||||
// The only technical detail we have is that we don't know that
|
||||
// PhysReg won't be clobbered by a reloaded stack slot that occurs
|
||||
// later in the instruction. In particular, consider 'op V1, V2'.
|
||||
// If V1 is available in physreg R0, we would choose to reuse it
|
||||
// here, instead of reloading it into the register the allocator
|
||||
// indicated (say R1). However, V2 might have to be reloaded
|
||||
// later, and it might indicate that it needs to live in R0. When
|
||||
// this occurs, we need to have information available that
|
||||
// indicates it is safe to use R1 for the reload instead of R0.
|
||||
//
|
||||
// To further complicate matters, we might conflict with an alias,
|
||||
// or R0 and R1 might not be compatible with each other. In this
|
||||
// case, we actually insert a reload for V1 in R1, ensuring that
|
||||
// we can get at R0 or its alias.
|
||||
ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
|
||||
VRM->getPhys(VirtReg), VirtReg);
|
||||
if (isTied)
|
||||
// Only mark it clobbered if this is a use&def operand.
|
||||
ReusedOperands.markClobbered(PhysReg);
|
||||
++NumReused;
|
||||
|
||||
if (MI.getOperand(i).isKill() &&
|
||||
ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
|
||||
|
||||
// The store of this spilled value is potentially dead, but we
|
||||
// won't know for certain until we've confirmed that the re-use
|
||||
// above is valid, which means waiting until the other operands
|
||||
// are processed. For now we just track the spill slot, we'll
|
||||
// remove it after the other operands are processed if valid.
|
||||
|
||||
PotentialDeadStoreSlots.push_back(ReuseSlot);
|
||||
}
|
||||
|
||||
// Mark is isKill if it's there no other uses of the same virtual
|
||||
// register and it's not a two-address operand. IsKill will be
|
||||
// unset if reg is reused.
|
||||
if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
|
||||
MI.getOperand(i).setIsKill();
|
||||
KilledMIRegs.insert(VirtReg);
|
||||
}
|
||||
|
||||
continue;
|
||||
} // CanReuse
|
||||
|
||||
// Otherwise we have a situation where we have a two-address instruction
|
||||
// whose mod/ref operand needs to be reloaded. This reload is already
|
||||
// available in some register "PhysReg", but if we used PhysReg as the
|
||||
// operand to our 2-addr instruction, the instruction would modify
|
||||
// PhysReg. This isn't cool if something later uses PhysReg and expects
|
||||
// to get its initial value.
|
||||
//
|
||||
// To avoid this problem, and to avoid doing a load right after a store,
|
||||
// we emit a copy from PhysReg into the designated register for this
|
||||
// operand.
|
||||
//
|
||||
// This case also applies to an earlyclobber'd PhysReg.
|
||||
unsigned DesignatedReg = VRM->getPhys(VirtReg);
|
||||
assert(DesignatedReg && "Must map virtreg to physreg!");
|
||||
|
||||
// Note that, if we reused a register for a previous operand, the
|
||||
// register we want to reload into might not actually be
|
||||
// available. If this occurs, use the register indicated by the
|
||||
// reuser.
|
||||
if (ReusedOperands.hasReuses())
|
||||
DesignatedReg = ReusedOperands.
|
||||
GetRegForReload(VirtReg, DesignatedReg, &MI, Spills,
|
||||
MaybeDeadStores, RegKills, KillOps, *VRM);
|
||||
|
||||
// If the mapped designated register is actually the physreg we have
|
||||
// incoming, we don't need to inserted a dead copy.
|
||||
if (DesignatedReg == PhysReg) {
|
||||
// If this stack slot value is already available, reuse it!
|
||||
if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
|
||||
DEBUG(dbgs() << "Reusing RM#"
|
||||
<< ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
|
||||
else
|
||||
DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
|
||||
DEBUG(dbgs() << " from physreg " << TRI->getName(PhysReg)
|
||||
<< " for vreg" << VirtReg
|
||||
<< " instead of reloading into same physreg.\n");
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
MI.getOperand(i).setSubReg(0);
|
||||
ReusedOperands.markClobbered(RReg);
|
||||
++NumReused;
|
||||
continue;
|
||||
}
|
||||
|
||||
MRI->setPhysRegUsed(DesignatedReg);
|
||||
ReusedOperands.markClobbered(DesignatedReg);
|
||||
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
MachineInstr *CopyMI = BuildMI(*MBB, InsertLoc, MI.getDebugLoc(),
|
||||
TII->get(TargetOpcode::COPY),
|
||||
DesignatedReg).addReg(PhysReg);
|
||||
CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
|
||||
UpdateKills(*CopyMI, TRI, RegKills, KillOps);
|
||||
|
||||
// This invalidates DesignatedReg.
|
||||
Spills.ClobberPhysReg(DesignatedReg);
|
||||
|
||||
Spills.addAvailable(ReuseSlot, DesignatedReg);
|
||||
unsigned RReg =
|
||||
SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
MI.getOperand(i).setSubReg(0);
|
||||
DEBUG(dbgs() << '\t' << *prior(MII));
|
||||
++NumReused;
|
||||
continue;
|
||||
} // if (PhysReg)
|
||||
|
||||
// Otherwise, reload it and remember that we have it.
|
||||
PhysReg = VRM->getPhys(VirtReg);
|
||||
assert(PhysReg && "Must map virtreg to physreg!");
|
||||
|
||||
// Note that, if we reused a register for a previous operand, the
|
||||
// register we want to reload into might not actually be
|
||||
// available. If this occurs, use the register indicated by the
|
||||
// reuser.
|
||||
if (ReusedOperands.hasReuses())
|
||||
PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
|
||||
|
||||
MRI->setPhysRegUsed(PhysReg);
|
||||
ReusedOperands.markClobbered(PhysReg);
|
||||
if (AvoidReload)
|
||||
++NumAvoided;
|
||||
else {
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(MII, MBB->begin(), PhysReg, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
|
||||
if (DoReMat) {
|
||||
ReMaterialize(*MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, *VRM);
|
||||
} else {
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC,TRI);
|
||||
MachineInstr *LoadMI = prior(InsertLoc);
|
||||
VRM->addSpillSlotUse(SSorRMId, LoadMI);
|
||||
++NumLoads;
|
||||
DistanceMap.insert(std::make_pair(LoadMI, DistanceMap.size()));
|
||||
}
|
||||
// This invalidates PhysReg.
|
||||
Spills.ClobberPhysReg(PhysReg);
|
||||
|
||||
// Any stores to this stack slot are not dead anymore.
|
||||
if (!DoReMat)
|
||||
MaybeDeadStores[SSorRMId] = NULL;
|
||||
Spills.addAvailable(SSorRMId, PhysReg);
|
||||
// Assumes this is the last use. IsKill will be unset if reg is reused
|
||||
// unless it's a two-address operand.
|
||||
if (!MI.isRegTiedToDefOperand(i) &&
|
||||
KilledMIRegs.count(VirtReg) == 0) {
|
||||
MI.getOperand(i).setIsKill();
|
||||
KilledMIRegs.insert(VirtReg);
|
||||
}
|
||||
|
||||
UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
|
||||
DEBUG(dbgs() << '\t' << *prior(InsertLoc));
|
||||
}
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
MI.getOperand(i).setSubReg(0);
|
||||
}
|
||||
|
||||
// Ok - now we can remove stores that have been confirmed dead.
|
||||
for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
|
||||
// This was the last use and the spilled value is still available
|
||||
// for reuse. That means the spill was unnecessary!
|
||||
int PDSSlot = PotentialDeadStoreSlots[j];
|
||||
MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
|
||||
if (DeadStore) {
|
||||
DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
|
||||
InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
|
||||
VRM->RemoveMachineInstrFromMaps(DeadStore);
|
||||
MBB->erase(DeadStore);
|
||||
MaybeDeadStores[PDSSlot] = NULL;
|
||||
++NumDSE;
|
||||
}
|
||||
}
|
||||
|
||||
ProcessUses(MI, Spills, MaybeDeadStores, RegKills, ReusedOperands, KillOps);
|
||||
|
||||
DEBUG(dbgs() << '\t' << MI);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user