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https://github.com/RPCSX/llvm.git
synced 2024-12-08 20:29:13 +00:00
change getSizeOfImm and getBaseOpcodeFor to just take
TSFlags directly instead of a TargetInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95405 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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daa4555793
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@ -566,7 +566,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(*Desc);
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc->TSFlags);
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switch (Desc->TSFlags & X86II::FormMask) {
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default:
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llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
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@ -596,7 +596,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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case X86::MOVPC32r: {
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// This emits the "call" portion of this pseudo instruction.
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MCE.emitByte(BaseOpcode);
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emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
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emitConstant(0, X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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// Remember PIC base.
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PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
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X86JITInfo *JTI = TM.getJITInfo();
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@ -641,9 +641,9 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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// Fix up immediate operand for pc relative calls.
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intptr_t Imm = (intptr_t)MO.getImm();
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Imm = Imm - MCE.getCurrentPCValue() - 4;
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emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
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emitConstant(Imm, X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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} else
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emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
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emitConstant(MO.getImm(), X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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}
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@ -654,7 +654,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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break;
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO1.isImm()) {
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emitConstant(MO1.getImm(), Size);
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break;
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@ -687,7 +687,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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CurOp += 2;
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if (CurOp != NumOps)
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emitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(Desc));
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X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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}
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case X86II::MRMDestMem: {
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@ -698,7 +698,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps)
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emitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(Desc));
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X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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}
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@ -709,7 +709,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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CurOp += 2;
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if (CurOp != NumOps)
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emitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(Desc));
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X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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case X86II::MRMSrcMem: {
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@ -722,7 +722,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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AddrOperands = X86AddrNumOperands;
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intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
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X86InstrInfo::sizeOfImm(Desc) : 0;
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X86InstrInfo::getSizeOfImm(Desc->TSFlags) : 0;
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
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@ -730,7 +730,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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CurOp += AddrOperands + 1;
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if (CurOp != NumOps)
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emitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(Desc));
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X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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}
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@ -765,7 +765,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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break;
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO1.isImm()) {
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emitConstant(MO1.getImm(), Size);
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break;
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@ -794,7 +794,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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case X86II::MRM6m: case X86II::MRM7m: {
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intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
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(MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
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X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
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X86InstrInfo::getSizeOfImm(Desc->TSFlags) : 4) : 0;
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
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@ -805,7 +805,7 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
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break;
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const MachineOperand &MO = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO.isImm()) {
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emitConstant(MO.getImm(), Size);
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break;
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@ -7033,8 +7033,8 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
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// Large code-model.
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const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
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const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
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const unsigned char JMP64r = TII->getBaseOpcodeForOpcode(X86::JMP64r);
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const unsigned char MOV64ri = TII->getBaseOpcodeForOpcode(X86::MOV64ri);
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const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
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const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
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@ -7129,7 +7129,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
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DAG.getConstant(10, MVT::i32));
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Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
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const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
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const unsigned char MOV32ri = TII->getBaseOpcodeForOpcode(X86::MOV32ri);
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const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
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OutChains[0] = DAG.getStore(Root, dl,
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DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
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@ -7139,7 +7139,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
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DAG.getConstant(1, MVT::i32));
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OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
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const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
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const unsigned char JMP = TII->getBaseOpcodeForOpcode(X86::JMP);
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Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
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DAG.getConstant(5, MVT::i32));
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OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
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@ -3014,16 +3014,6 @@ isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
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}
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unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
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switch (Desc->TSFlags & X86II::ImmMask) {
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case X86II::Imm8: return 1;
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case X86II::Imm16: return 2;
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case X86II::Imm32: return 4;
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case X86II::Imm64: return 8;
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default: llvm_unreachable("Immediate size not set!");
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return 0;
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}
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}
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/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
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/// e.g. r8, xmm8, etc.
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@ -3400,7 +3390,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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case X86::MOVPC32r: {
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// This emits the "call" portion of this pseudo instruction.
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++FinalSize;
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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break;
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}
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}
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@ -3418,7 +3408,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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} else if (MO.isSymbol()) {
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FinalSize += sizeExternalSymbolAddress(false);
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} else if (MO.isImm()) {
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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} else {
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llvm_unreachable("Unknown RawFrm operand!");
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}
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@ -3431,7 +3421,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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if (CurOp != NumOps) {
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO1.isImm())
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FinalSize += sizeConstant(Size);
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else {
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@ -3456,7 +3446,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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CurOp += 2;
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if (CurOp != NumOps) {
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++CurOp;
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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}
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break;
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}
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@ -3466,7 +3456,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps) {
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++CurOp;
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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}
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break;
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}
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@ -3477,7 +3467,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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CurOp += 2;
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if (CurOp != NumOps) {
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++CurOp;
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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}
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break;
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@ -3494,7 +3484,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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CurOp += AddrOperands + 1;
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if (CurOp != NumOps) {
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++CurOp;
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FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
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FinalSize += sizeConstant(X86InstrInfo::getSizeOfImm(Desc->TSFlags));
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}
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break;
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}
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@ -3519,7 +3509,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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if (CurOp != NumOps) {
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO1.isImm())
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FinalSize += sizeConstant(Size);
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else {
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@ -3549,7 +3539,7 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
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if (CurOp != NumOps) {
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const MachineOperand &MO = MI.getOperand(CurOp++);
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unsigned Size = X86InstrInfo::sizeOfImm(Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(Desc->TSFlags);
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if (MO.isImm())
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FinalSize += sizeConstant(Size);
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else {
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@ -640,11 +640,11 @@ public:
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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//
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static unsigned char getBaseOpcodeFor(const TargetInstrDesc &TID) {
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return TID.TSFlags >> X86II::OpcodeShift;
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static unsigned char getBaseOpcodeFor(unsigned TSFlags) {
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return TSFlags >> X86II::OpcodeShift;
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}
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unsigned char getBaseOpcodeFor(unsigned Opcode) const {
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return getBaseOpcodeFor(get(Opcode));
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unsigned char getBaseOpcodeForOpcode(unsigned Opcode) const {
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return getBaseOpcodeFor(get(Opcode).TSFlags);
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}
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static bool isX86_64NonExtLowByteReg(unsigned reg) {
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@ -652,7 +652,15 @@ public:
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reg == X86::SIL || reg == X86::DIL);
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}
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static unsigned sizeOfImm(const TargetInstrDesc *Desc);
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static unsigned getSizeOfImm(unsigned TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8: return 1;
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case X86II::Imm16: return 2;
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case X86II::Imm32: return 4;
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case X86II::Imm64: return 8;
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}
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}
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static bool isX86_64ExtendedReg(const MachineOperand &MO);
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static unsigned determineREX(const MachineInstr &MI);
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@ -366,7 +366,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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// FIXME: Can we kill off MRMInitReg??
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
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unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(TSFlags);
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switch (TSFlags & X86II::FormMask) {
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default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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@ -387,7 +387,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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const MCOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isImm()) {
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unsigned Size = X86InstrInfo::sizeOfImm(&Desc);
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unsigned Size = X86InstrInfo::getSizeOfImm(TSFlags);
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EmitConstant(MO1.getImm(), Size, OS);
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break;
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}
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@ -403,7 +403,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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X86InstrInfo::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMDestMem:
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@ -414,7 +414,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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X86InstrInfo::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMSrcReg:
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@ -424,7 +424,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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X86InstrInfo::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMSrcMem: {
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@ -440,14 +440,14 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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// FIXME: What is this actually doing?
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intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
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X86InstrInfo::sizeOfImm(&Desc) : 0;
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X86InstrInfo::getSizeOfImm(TSFlags) : 0;
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EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
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PCAdj, OS);
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CurOp += AddrOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86InstrInfo::sizeOfImm(&Desc), OS);
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X86InstrInfo::getSizeOfImm(TSFlags), OS);
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break;
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}
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