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[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -10390,10 +10390,24 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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SmallVector<SDValue, 8> Opnds;
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unsigned BuildVecNumElts = N0.getNumOperands();
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N0.getOperand(i));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N1.getOperand(i));
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EVT SclTy0 = N0.getOperand(0)->getValueType(0);
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EVT SclTy1 = N1.getOperand(0)->getValueType(0);
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if (SclTy0.isFloatingPoint()) {
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N0.getOperand(i));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N1.getOperand(i));
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} else {
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// If BUILD_VECTOR are from built from integer, they may have different
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// operand types. Get the smaller type and truncate all operands to it.
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EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
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N0.getOperand(i)));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
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N1.getOperand(i)));
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}
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
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}
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@ -42,4 +42,18 @@ define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
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%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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ret <8 x i16> %c
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}
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}
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; There is an optimization in DAG Combiner as following:
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; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
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; -> (BUILD_VECTOR A, B, ..., C, D, ...)
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; This case checks when A,B and C,D are different types, there should be no
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; assertion failure.
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define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
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; CHECK-LABEL: concat_2_build_vector:
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; CHECK: movi
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%vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
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%vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
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%shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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