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R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190575 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,7 +19,8 @@ def CC_SI : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
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SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15
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SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
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SGPR16
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]>>>,
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CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
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@ -724,5 +724,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(SAMPLED)
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NODE_NAME_CASE(SAMPLEL)
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NODE_NAME_CASE(STORE_MSKOR)
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NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
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}
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}
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@ -160,6 +160,7 @@ enum {
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FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
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STORE_MSKOR,
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LOAD_CONSTANT,
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TBUFFER_STORE_FORMAT,
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LAST_AMDGPU_ISD_NUMBER
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};
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@ -86,6 +86,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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@ -463,6 +465,43 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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Op.getOperand(3));
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}
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}
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case ISD::INTRINSIC_VOID:
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SDValue Chain = Op.getOperand(0);
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unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::SI_tbuffer_store: {
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SDLoc DL(Op);
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SDValue Ops [] = {
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Chain,
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ResourceDescriptorToi128(Op.getOperand(2), DAG),
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Op.getOperand(3),
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Op.getOperand(4),
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Op.getOperand(5),
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Op.getOperand(6),
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Op.getOperand(7),
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Op.getOperand(8),
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Op.getOperand(9),
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Op.getOperand(10),
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Op.getOperand(11),
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Op.getOperand(12),
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Op.getOperand(13),
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Op.getOperand(14)
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};
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EVT VT = Op.getOperand(3).getValueType();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo(),
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MachineMemOperand::MOStore,
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VT.getSizeInBits() / 8, 4);
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return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
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Op->getVTList(), Ops,
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sizeof(Ops)/sizeof(Ops[0]), VT, MMO);
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}
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default:
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break;
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}
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}
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return SDValue();
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}
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@ -21,6 +21,25 @@ def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
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[SDNPMayLoad, SDNPMemOperand]
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>;
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def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
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SDTypeProfile<0, 13,
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[SDTCisVT<0, i128>, // rsrc(SGPR)
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SDTCisVT<1, iAny>, // vdata(VGPR)
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SDTCisVT<2, i32>, // num_channels(imm)
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SDTCisVT<3, i32>, // vaddr(VGPR)
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SDTCisVT<4, i32>, // soffset(SGPR)
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SDTCisVT<5, i32>, // inst_offset(imm)
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SDTCisVT<6, i32>, // dfmt(imm)
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SDTCisVT<7, i32>, // nfmt(imm)
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SDTCisVT<8, i32>, // offen(imm)
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SDTCisVT<9, i32>, // idxen(imm)
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SDTCisVT<10, i32>, // glc(imm)
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SDTCisVT<11, i32>, // slc(imm)
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SDTCisVT<12, i32> // tfe(imm)
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]>,
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[SDNPMayStore, SDNPMemOperand, SDNPHasChain]
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>;
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def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, i128>, SDTCisVT<2, i16>,
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SDTCisVT<3, i32>]>
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@ -65,6 +84,14 @@ def IMM8bitDWORD : ImmLeaf <
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}]>
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>;
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def as_i1imm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
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}]>;
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def as_i8imm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
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}]>;
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def as_i16imm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
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}]>;
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@ -477,10 +477,10 @@ def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
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//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
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//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
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def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>;
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//def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>;
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//def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>;
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//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>;
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//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>;
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def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>;
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def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>;
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def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
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def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
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let mayLoad = 1 in {
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@ -1881,6 +1881,27 @@ defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
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defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
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defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
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//===----------------------------------------------------------------------===//
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// MTBUF Patterns
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//===----------------------------------------------------------------------===//
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// TBUFFER_STORE_FORMAT_*, addr64=0
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class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
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(SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
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i32:$soffset, imm:$inst_offset, imm:$dfmt,
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imm:$nfmt, imm:$offen, imm:$idxen,
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imm:$glc, imm:$slc, imm:$tfe),
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(opcode
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$vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
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(as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
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(as_i1imm $slc), (as_i1imm $tfe), $soffset)
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>;
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def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
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def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
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def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
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def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
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/********** ====================== **********/
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/********** Indirect adressing **********/
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/********** ====================== **********/
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@ -20,6 +20,24 @@ let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
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// Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
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def int_SI_tbuffer_store : Intrinsic <
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[],
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
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llvm_i32_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // dfmt(imm)
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llvm_i32_ty, // nfmt(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[]>;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_sample : Sample;
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test/CodeGen/R600/llvm.SI.tbuffer.store.ll
Normal file
44
test/CodeGen/R600/llvm.SI.tbuffer.store.ll
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@ -0,0 +1,44 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK_LABEL: @test1
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;CHECK: TBUFFER_STORE_FORMAT_XYZW {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 32, -1, 0, -1, 0, 14, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0
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define void @test1(i32 %a1, i32 %vaddr) {
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%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
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call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
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i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1,
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i32 1, i32 0)
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ret void
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}
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;CHECK_LABEL: @test2
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;CHECK: TBUFFER_STORE_FORMAT_XYZ {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 24, -1, 0, -1, 0, 13, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0
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define void @test2(i32 %a1, i32 %vaddr) {
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%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
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call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
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i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1,
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i32 1, i32 0)
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ret void
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}
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;CHECK_LABEL: @test3
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;CHECK: TBUFFER_STORE_FORMAT_XY {{VGPR[0-9]+_VGPR[0-9]+}}, 16, -1, 0, -1, 0, 11, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0
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define void @test3(i32 %a1, i32 %vaddr) {
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%vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
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call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata,
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i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1,
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i32 1, i32 0)
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ret void
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}
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;CHECK_LABEL: @test4
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;CHECK: TBUFFER_STORE_FORMAT_X {{VGPR[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{VGPR[0-9]+}}, {{SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+_SGPR[0-9]+}}, -1, 0, 0
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define void @test4(i32 %vdata, i32 %vaddr) {
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
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i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1,
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i32 1, i32 0)
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ret void
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}
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declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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declare void @llvm.SI.tbuffer.store.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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