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[ARM] GlobalISel: Simplify inst selector code. NFC
Refactor CmpHelper into something simpler. It was overkill to use templates for this - instead, use a simple CmpConstants structure to hold the opcodes and other constants that are different when selecting int / float / double comparisons. Also, extract some of the helpers that were in CmpHelper into ARMInstructionSelector and make use of some of them when selecting other things than just compares. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307766 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus
parent
3870ce243f
commit
a3db45981c
@ -44,16 +44,32 @@ public:
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private:
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bool selectImpl(MachineInstr &I) const;
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template <typename T> struct CmpHelper;
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struct CmpConstants;
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struct InsertInfo;
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template <typename T>
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bool selectCmp(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const;
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bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
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MachineRegisterInfo &MRI) const;
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bool selectSelect(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const;
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// Helper for inserting a comparison sequence that sets \p ResReg to either 1
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// if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
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// \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
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bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
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ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
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unsigned PrevRes) const;
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// Set \p DestReg to \p Constant.
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void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
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bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
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// Check if the types match and both operands have the expected size and
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// register bank.
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bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
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unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
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// Check if the register has the expected size and register bank.
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bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
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unsigned ExpectedRegBankID) const;
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const ARMBaseInstrInfo &TII;
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const ARMBaseRegisterInfo &TRI;
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@ -326,212 +342,110 @@ getComparePreds(CmpInst::Predicate Pred) {
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return Preds;
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}
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template <typename T> struct ARMInstructionSelector::CmpHelper {
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CmpHelper(const ARMInstructionSelector &Selector, MachineInstrBuilder &MIB,
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const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
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: MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
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DbgLoc(MIB->getDebugLoc()), TII(TII), MRI(MRI), TRI(TRI), RBI(RBI),
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Selector(Selector) {}
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struct ARMInstructionSelector::CmpConstants {
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CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank,
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unsigned OpSize)
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: ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
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OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
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// The opcode used for performing the comparison.
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static const unsigned ComparisonOpcode;
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const unsigned ComparisonOpcode;
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// The opcode used for reading the flags set by the comparison. May be
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// ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
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static const unsigned ReadFlagsOpcode;
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// The opcode used for selecting the result register, based on the value
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// of the flags.
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static const unsigned SetResultOpcode = ARM::MOVCCi;
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const unsigned ReadFlagsOpcode;
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// The assumed register bank ID for the operands.
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static const unsigned OperandRegBankID;
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const unsigned OperandRegBankID;
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// The assumed size in bits for the operands.
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static const unsigned OperandSize;
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// The assumed register bank ID for the result.
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static const unsigned ResultRegBankID = ARM::GPRRegBankID;
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unsigned getZeroRegister() {
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unsigned Reg = MRI.createVirtualRegister(&ARM::GPRRegClass);
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putConstant(Reg, 0);
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return Reg;
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}
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void putConstant(unsigned DestReg, unsigned Constant) {
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(void)BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVi))
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.addDef(DestReg)
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.addImm(Constant)
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.add(predOps(ARMCC::AL))
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.add(condCodeOp());
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}
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bool insertComparison(unsigned ResReg, ARMCC::CondCodes Cond, unsigned LHSReg,
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unsigned RHSReg, unsigned PrevRes) {
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// Perform the comparison.
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auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ComparisonOpcode))
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.addUse(LHSReg)
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.addUse(RHSReg)
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.add(predOps(ARMCC::AL));
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if (!Selector.constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
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return false;
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// Read the comparison flags (if necessary).
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if (ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
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auto ReadI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ReadFlagsOpcode))
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.add(predOps(ARMCC::AL));
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if (!Selector.constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
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return false;
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}
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// Select either 1 or the previous result based on the value of the flags.
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auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(SetResultOpcode))
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.addDef(ResReg)
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.addUse(PrevRes)
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.addImm(1)
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.add(predOps(Cond, ARM::CPSR));
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if (!Selector.constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
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return false;
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return true;
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}
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bool validateOpRegs(unsigned LHSReg, unsigned RHSReg) {
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return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
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validateOpReg(LHSReg, MRI, TRI, RBI) &&
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validateOpReg(RHSReg, MRI, TRI, RBI);
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}
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bool validateResReg(unsigned ResReg) {
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if (MRI.getType(ResReg).getSizeInBits() != 1) {
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DEBUG(dbgs() << "Unsupported size for comparison operand");
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return false;
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}
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if (RBI.getRegBank(ResReg, MRI, TRI)->getID() != ResultRegBankID) {
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DEBUG(dbgs() << "Unsupported register bank for comparison operand");
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return false;
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}
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return true;
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}
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private:
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bool validateOpReg(unsigned OpReg, MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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if (MRI.getType(OpReg).getSizeInBits() != OperandSize) {
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DEBUG(dbgs() << "Unsupported size for comparison operand");
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return false;
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}
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if (RBI.getRegBank(OpReg, MRI, TRI)->getID() != OperandRegBankID) {
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DEBUG(dbgs() << "Unsupported register bank for comparison operand");
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return false;
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}
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return true;
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}
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MachineBasicBlock &MBB;
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MachineBasicBlock::instr_iterator InsertBefore;
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const DebugLoc &DbgLoc;
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const ARMBaseInstrInfo &TII;
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MachineRegisterInfo &MRI;
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const TargetRegisterInfo &TRI;
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const RegisterBankInfo &RBI;
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const ARMInstructionSelector &Selector;
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const unsigned OperandSize;
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};
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// Specialize the opcode to be used for comparing different types of operands.
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<int>::ComparisonOpcode =
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ARM::CMPrr;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::ComparisonOpcode =
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ARM::VCMPS;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::ComparisonOpcode =
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ARM::VCMPD;
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struct ARMInstructionSelector::InsertInfo {
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InsertInfo(MachineInstrBuilder &MIB)
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: MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
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DbgLoc(MIB->getDebugLoc()) {}
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// Specialize the opcode to be used for reading the comparison flags for
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// different types of operands.
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<int>::ReadFlagsOpcode =
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ARM::INSTRUCTION_LIST_END;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::ReadFlagsOpcode =
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ARM::FMSTAT;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::ReadFlagsOpcode =
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ARM::FMSTAT;
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MachineBasicBlock &MBB;
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const MachineBasicBlock::instr_iterator InsertBefore;
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const DebugLoc &DbgLoc;
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};
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// Specialize the register bank where the operands of the comparison are assumed
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// to live.
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<int>::OperandRegBankID =
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ARM::GPRRegBankID;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::OperandRegBankID =
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ARM::FPRRegBankID;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::OperandRegBankID =
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ARM::FPRRegBankID;
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void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
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unsigned Constant) const {
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(void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))
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.addDef(DestReg)
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.addImm(Constant)
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.add(predOps(ARMCC::AL))
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.add(condCodeOp());
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}
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// Specialize the size that the operands of the comparison are assumed to have.
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<int>::OperandSize = 32;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<float>::OperandSize = 32;
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template <>
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const unsigned ARMInstructionSelector::CmpHelper<double>::OperandSize = 64;
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bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
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unsigned LHSReg, unsigned RHSReg,
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unsigned ExpectedSize,
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unsigned ExpectedRegBankID) const {
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return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
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validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
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validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
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}
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template <typename T>
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bool ARMInstructionSelector::selectCmp(MachineInstrBuilder &MIB,
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const ARMBaseInstrInfo &TII,
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MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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auto Helper = CmpHelper<T>(*this, MIB, TII, MRI, TRI, RBI);
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bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
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unsigned ExpectedSize,
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unsigned ExpectedRegBankID) const {
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if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
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DEBUG(dbgs() << "Unexpected size for register");
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return false;
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}
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if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
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DEBUG(dbgs() << "Unexpected register bank for register");
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return false;
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}
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return true;
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}
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bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
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MachineInstrBuilder &MIB,
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MachineRegisterInfo &MRI) const {
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const InsertInfo I(MIB);
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auto ResReg = MIB->getOperand(0).getReg();
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if (!Helper.validateResReg(ResReg))
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if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
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return false;
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auto Cond =
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static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
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if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
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Helper.putConstant(ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
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putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
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MIB->eraseFromParent();
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return true;
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}
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auto LHSReg = MIB->getOperand(2).getReg();
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auto RHSReg = MIB->getOperand(3).getReg();
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if (!Helper.validateOpRegs(LHSReg, RHSReg))
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if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
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Helper.OperandRegBankID))
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return false;
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auto ARMConds = getComparePreds(Cond);
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auto ZeroReg = Helper.getZeroRegister();
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auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
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putConstant(I, ZeroReg, 0);
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if (ARMConds.second == ARMCC::AL) {
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// Simple case, we only need one comparison and we're done.
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if (!Helper.insertComparison(ResReg, ARMConds.first, LHSReg, RHSReg,
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ZeroReg))
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if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
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ZeroReg))
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return false;
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} else {
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// Not so simple, we need two successive comparisons.
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auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
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if (!Helper.insertComparison(IntermediateRes, ARMConds.first, LHSReg,
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RHSReg, ZeroReg))
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if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
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RHSReg, ZeroReg))
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return false;
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if (!Helper.insertComparison(ResReg, ARMConds.second, LHSReg, RHSReg,
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IntermediateRes))
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if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
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IntermediateRes))
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return false;
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}
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@ -539,19 +453,50 @@ bool ARMInstructionSelector::selectCmp(MachineInstrBuilder &MIB,
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return true;
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}
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bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
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unsigned ResReg,
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ARMCC::CondCodes Cond,
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unsigned LHSReg, unsigned RHSReg,
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unsigned PrevRes) const {
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// Perform the comparison.
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auto CmpI =
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BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
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.addUse(LHSReg)
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.addUse(RHSReg)
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.add(predOps(ARMCC::AL));
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if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
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return false;
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// Read the comparison flags (if necessary).
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if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
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auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
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TII.get(Helper.ReadFlagsOpcode))
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.add(predOps(ARMCC::AL));
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if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
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return false;
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}
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// Select either 1 or the previous result based on the value of the flags.
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auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))
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.addDef(ResReg)
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.addUse(PrevRes)
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.addImm(1)
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.add(predOps(Cond, ARM::CPSR));
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if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
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return false;
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return true;
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}
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bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
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const ARMBaseInstrInfo &TII,
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MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineRegisterInfo &MRI) const {
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auto &MBB = *MIB->getParent();
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auto InsertBefore = std::next(MIB->getIterator());
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auto &DbgLoc = MIB->getDebugLoc();
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// Compare the condition to 0.
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auto CondReg = MIB->getOperand(1).getReg();
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assert(MRI.getType(CondReg).getSizeInBits() == 1 &&
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RBI.getRegBank(CondReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
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assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
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"Unsupported types for select operation");
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auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))
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.addUse(CondReg)
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@ -565,11 +510,8 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
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auto ResReg = MIB->getOperand(0).getReg();
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auto TrueReg = MIB->getOperand(2).getReg();
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auto FalseReg = MIB->getOperand(3).getReg();
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assert(MRI.getType(ResReg) == MRI.getType(TrueReg) &&
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MRI.getType(TrueReg) == MRI.getType(FalseReg) &&
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MRI.getType(FalseReg).getSizeInBits() == 32 &&
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RBI.getRegBank(TrueReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
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RBI.getRegBank(FalseReg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
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assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
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validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
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"Unsupported types for select operation");
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auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))
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.addDef(ResReg)
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@ -684,26 +626,30 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
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return selectCopy(I, TII, MRI, TRI, RBI);
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}
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case G_SELECT:
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return selectSelect(MIB, TII, MRI, TRI, RBI);
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case G_ICMP:
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return selectCmp<int>(MIB, TII, MRI, TRI, RBI);
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return selectSelect(MIB, MRI);
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case G_ICMP: {
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CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,
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ARM::GPRRegBankID, 32);
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return selectCmp(Helper, MIB, MRI);
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}
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case G_FCMP: {
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assert(TII.getSubtarget().hasVFP2() && "Can't select fcmp without VFP");
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unsigned OpReg = I.getOperand(2).getReg();
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unsigned Size = MRI.getType(OpReg).getSizeInBits();
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if (Size == 32)
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return selectCmp<float>(MIB, TII, MRI, TRI, RBI);
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if (Size == 64) {
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if (TII.getSubtarget().isFPOnlySP()) {
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DEBUG(dbgs() << "Subtarget only supports single precision");
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return false;
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}
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return selectCmp<double>(MIB, TII, MRI, TRI, RBI);
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if (Size == 64 && TII.getSubtarget().isFPOnlySP()) {
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DEBUG(dbgs() << "Subtarget only supports single precision");
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return false;
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}
|
||||
if (Size != 32 && Size != 64) {
|
||||
DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
|
||||
return false;
|
||||
}
|
||||
|
||||
DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
|
||||
return false;
|
||||
CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
|
||||
ARM::FPRRegBankID, Size);
|
||||
return selectCmp(Helper, MIB, MRI);
|
||||
}
|
||||
case G_GEP:
|
||||
I.setDesc(TII.get(ARM::ADDrr));
|
||||
@ -717,11 +663,10 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
|
||||
break;
|
||||
case G_CONSTANT: {
|
||||
unsigned Reg = I.getOperand(0).getReg();
|
||||
if (MRI.getType(Reg).getSizeInBits() != 32)
|
||||
|
||||
if (!validReg(MRI, Reg, 32, ARM::GPRRegBankID))
|
||||
return false;
|
||||
|
||||
assert(RBI.getRegBank(Reg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
|
||||
"Expected constant to live in a GPR");
|
||||
I.setDesc(TII.get(ARM::MOVi));
|
||||
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user