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Cleanup

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2008-10-10 10:14:15 +00:00
parent 7238cfaca0
commit a43e51d0fe
1 changed files with 12 additions and 12 deletions
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24
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -44,15 +44,15 @@ public:
bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2); bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base, bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset); SDValue &Offset);
/// InstructionSelect - This callback is invoked by /// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect(); virtual void InstructionSelect();
virtual const char *getPassName() const { virtual const char *getPassName() const {
return "SPARC DAG->DAG Pattern Instruction Selection"; return "SPARC DAG->DAG Pattern Instruction Selection";
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "SparcGenDAGISel.inc" #include "SparcGenDAGISel.inc"
}; };
@ -62,7 +62,7 @@ public:
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SparcDAGToDAGISel::InstructionSelect() { void SparcDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump()); DEBUG(BB->dump());
// Select target instructions for the DAG. // Select target instructions for the DAG.
SelectRoot(); SelectRoot();
CurDAG->RemoveDeadNodes(); CurDAG->RemoveDeadNodes();
@ -78,11 +78,11 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
if (Addr.getOpcode() == ISD::TargetExternalSymbol || if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls. return false; // direct calls.
if (Addr.getOpcode() == ISD::ADD) { if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
if (Predicate_simm13(CN)) { if (Predicate_simm13(CN)) {
if (FrameIndexSDNode *FIN = if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
// Constant offset from frame ref. // Constant offset from frame ref.
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@ -115,7 +115,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
if (Addr.getOpcode() == ISD::TargetExternalSymbol || if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls. return false; // direct calls.
if (Addr.getOpcode() == ISD::ADD) { if (Addr.getOpcode() == ISD::ADD) {
if (isa<ConstantSDNode>(Addr.getOperand(1)) && if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).getNode())) Predicate_simm13(Addr.getOperand(1).getNode()))
@ -147,7 +147,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
SDValue DivRHS = N->getOperand(1); SDValue DivRHS = N->getOperand(1);
AddToISelQueue(DivLHS); AddToISelQueue(DivLHS);
AddToISelQueue(DivRHS); AddToISelQueue(DivRHS);
// Set the Y register to the high-part. // Set the Y register to the high-part.
SDValue TopPart; SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) { if (N->getOpcode() == ISD::SDIV) {
@ -163,7 +163,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
TopPart); TopPart);
} }
case ISD::MULHU: case ISD::MULHU:
case ISD::MULHS: { case ISD::MULHS: {
// FIXME: Handle mul by immediate. // FIXME: Handle mul by immediate.
@ -179,12 +179,12 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
return NULL; return NULL;
} }
} }
return SelectCode(Op); return SelectCode(Op);
} }
/// createSparcISelDag - This pass converts a legalized DAG into a /// createSparcISelDag - This pass converts a legalized DAG into a
/// SPARC-specific DAG, ready for instruction scheduling. /// SPARC-specific DAG, ready for instruction scheduling.
/// ///
FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {