RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-26 21:20:37 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Refactor some of the "disassembly-only" instructions into a base class. This

Browse Source 
reduces some code duplication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120326 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-29 22:15:03 +00:00
parent e9e973018a
commit a46a493c02
1 changed files with 21 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
lib/Target/ARM/ARMInstrThumb.td
View File

@ -136,44 +136,40 @@ def tADJCALLSTACKDOWN :
Requires<[IsThumb, IsThumb1Only]>;
}
class T1Disassembly<bits<2> op1, bits<8> op2>
: T1Encoding<0b101111> {
let Inst{9-8} = op1;
let Inst{7-0} = op2;
}
def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.110
let Inst{9-8} = 0b11;
let Inst{7-0} = 0x00;
}
T1Disassembly<0b11, 0x00>; // A8.6.110
def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.410
let Inst{9-8} = 0b11;
let Inst{7-0} = 0x10;
}
T1Disassembly<0b11, 0x10>; // A8.6.410
def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.408
let Inst{9-8} = 0b11;
let Inst{7-0} = 0x20;
}
T1Disassembly<0b11, 0x20>; // A8.6.408
def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.409
let Inst{9-8} = 0b11;
let Inst{7-0} = 0x30;
}
T1Disassembly<0b11, 0x30>; // A8.6.409
def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.157
let Inst{9-8} = 0b11;
let Inst{7-0} = 0x40;
T1Disassembly<0b11, 0x40>; // A8.6.157
// The i32imm operand $val can be used by a debugger to store more information
// about the breakpoint.
def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
[/* For disassembly only; pattern left blank */]>,
T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
// A8.6.22
bits<8> val;
let Inst{7-0} = val;
}
def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
@ -196,17 +192,6 @@ def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
let Inst{2-0} = 0b000;
}
// The i32imm operand $val can be used by a debugger to store more information
// about the breakpoint.
def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
// A8.6.22
bits<8> val;
let Inst{9-8} = 0b10;
let Inst{7-0} = val;
}
// Change Processor State is a system instruction -- for disassembly only.
// The singleton $opt operand contains the following information:
// opt{4-0} = mode ==> don't care