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Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes"

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This reverts commit r288916 as it is currently causing a crasher in
Halide. Reproducer on llvm.org/PR31323. While it might be that halide is
generating invalid IR, llc shouldn't crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Jasper 2016-12-09 09:04:51 +00:00
parent ff96f08e32
commit a47587665f
2 changed files with 10 additions and 38 deletions
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36
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2590,42 +2590,6 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
}
break;
}
case ISD::INSERT_VECTOR_ELT: {
SDValue InVec = Op.getOperand(0);
SDValue InVal = Op.getOperand(1);
SDValue EltNo = Op.getOperand(2);
ConstantSDNode *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
// If we know the element index, split the demand between the
// source vector and the inserted element.
KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
unsigned EltIdx = CEltNo->getZExtValue();
// If we demand the inserted element then add its common known bits.
if (DemandedElts[EltIdx]) {
computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
}
// If we demand the source vector then add its common known bits, ensuring
// that we don't demand the inserted element.
APInt VectorElts = DemandedElts & ~(APInt::getOneBitSet(NumElts, EltIdx));
if (!!VectorElts) {
computeKnownBits(InVec, KnownZero2, KnownOne2, VectorElts, Depth + 1);
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
}
} else {
// Unknown element index, so ignore DemandedElts and demand them all.
computeKnownBits(InVec, KnownZero, KnownOne, Depth + 1);
computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
}
break;
}
case ISD::BSWAP: {
computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
Depth + 1);

12
test/CodeGen/X86/known-bits-vector.ll
View File

@ -58,7 +58,11 @@ define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nou
; X32-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0
; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X32-NEXT: vpsrld $16, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X32-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0
; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_insert_uitofp:
@ -68,7 +72,11 @@ define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nou
; X64-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0
; X64-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X64-NEXT: vpsrld $16, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X64-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X64-NEXT: retq
%1 = zext i16 %a1 to i32
%2 = zext i16 %a2 to i32