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Don't add implicit regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4840 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
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if (isSigned) {
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// Emit a sign extension instruction...
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BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
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BuildMI(BB, ExtOpcode[Class], 0);
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} else {
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// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
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BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
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if (isSigned) {
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// Emit a sign extension instruction...
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BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
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BuildMI(BB, ExtOpcode[Class], 0);
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} else {
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// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
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BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
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