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Change MachineVerifier to work on LiveRange + LiveInterval
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192395 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
parent
5649e25ce8
commit
a4aed9ae39
@ -213,6 +213,10 @@ namespace {
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const LiveInterval &LI);
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void report(const char *msg, const MachineBasicBlock *MBB,
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const LiveInterval &LI);
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void report(const char *msg, const MachineFunction *MF,
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const LiveRange &LR);
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void report(const char *msg, const MachineBasicBlock *MBB,
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const LiveRange &LR);
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void verifyInlineAsm(const MachineInstr *MI);
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@ -225,9 +229,10 @@ namespace {
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void verifyLiveVariables();
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void verifyLiveIntervals();
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void verifyLiveInterval(const LiveInterval&);
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void verifyLiveIntervalValue(const LiveInterval&, VNInfo*);
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void verifyLiveIntervalSegment(const LiveInterval&,
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LiveInterval::const_iterator);
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void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned);
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void verifyLiveRangeSegment(const LiveRange&,
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const LiveRange::const_iterator I, unsigned);
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void verifyLiveRange(const LiveRange&, unsigned);
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void verifyStackFrame();
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};
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@ -433,6 +438,18 @@ void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
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*OS << ' ' << LI << '\n';
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
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const LiveRange &LR) {
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report(msg, MBB);
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*OS << "- liverange: " << LR << "\n";
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}
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void MachineVerifier::report(const char *msg, const MachineFunction *MF,
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const LiveRange &LR) {
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report(msg, MF);
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*OS << "- liverange: " << LR << "\n";
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}
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void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
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BBInfo &MInfo = MBBInfoMap[MBB];
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if (!MInfo.reachable) {
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@ -1339,21 +1356,22 @@ void MachineVerifier::verifyLiveIntervals() {
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verifyLiveInterval(*LI);
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}
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void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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VNInfo *VNI) {
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void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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const VNInfo *VNI,
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unsigned Reg) {
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if (VNI->isUnused())
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return;
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const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
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const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
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if (!DefVNI) {
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report("Valno not live at def and not marked unused", MF, LI);
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report("Valno not live at def and not marked unused", MF, LR);
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*OS << "Valno #" << VNI->id << '\n';
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return;
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}
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if (DefVNI != VNI) {
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report("Live segment at def has different valno", MF, LI);
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report("Live segment at def has different valno", MF, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " where valno #" << DefVNI->id << " is live\n";
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return;
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@ -1361,15 +1379,15 @@ void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
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if (!MBB) {
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report("Invalid definition index", MF, LI);
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report("Invalid definition index", MF, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LI << '\n';
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<< " in " << LR << '\n';
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return;
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}
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if (VNI->isPHIDef()) {
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if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
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report("PHIDef value is not defined at MBB start", MBB, LI);
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report("PHIDef value is not defined at MBB start", MBB, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< ", not at the beginning of BB#" << MBB->getNumber() << '\n';
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}
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@ -1379,136 +1397,139 @@ void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
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// Non-PHI def.
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const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
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if (!MI) {
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report("No instruction at def index", MBB, LI);
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report("No instruction at def index", MBB, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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return;
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}
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bool hasDef = false;
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bool isEarlyClobber = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || !MOI->isDef())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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if (MOI->getReg() != LI.reg)
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continue;
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} else {
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if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
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!TRI->hasRegUnit(MOI->getReg(), LI.reg))
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if (Reg != 0) {
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bool hasDef = false;
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bool isEarlyClobber = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || !MOI->isDef())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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if (MOI->getReg() != Reg)
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continue;
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} else {
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if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
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!TRI->hasRegUnit(MOI->getReg(), Reg))
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continue;
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}
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hasDef = true;
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if (MOI->isEarlyClobber())
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isEarlyClobber = true;
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}
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hasDef = true;
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if (MOI->isEarlyClobber())
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isEarlyClobber = true;
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}
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if (!hasDef) {
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report("Defining instruction does not modify register", MI);
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*OS << "Valno #" << VNI->id << " in " << LI << '\n';
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}
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if (!hasDef) {
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report("Defining instruction does not modify register", MI);
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*OS << "Valno #" << VNI->id << " in " << LR << '\n';
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}
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// Early clobber defs begin at USE slots, but other defs must begin at
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// DEF slots.
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if (isEarlyClobber) {
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if (!VNI->def.isEarlyClobber()) {
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report("Early clobber def must be at an early-clobber slot", MBB, LI);
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// Early clobber defs begin at USE slots, but other defs must begin at
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// DEF slots.
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if (isEarlyClobber) {
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if (!VNI->def.isEarlyClobber()) {
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report("Early clobber def must be at an early-clobber slot", MBB, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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}
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} else if (!VNI->def.isRegister()) {
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report("Non-PHI, non-early clobber def must be at a register slot",
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MBB, LR);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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}
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} else if (!VNI->def.isRegister()) {
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report("Non-PHI, non-early clobber def must be at a register slot",
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MBB, LI);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
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}
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}
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void
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MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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LiveInterval::const_iterator I) {
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const VNInfo *VNI = I->valno;
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void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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const LiveRange::const_iterator I,
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unsigned Reg) {
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const LiveRange::Segment &S = *I;
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const VNInfo *VNI = S.valno;
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assert(VNI && "Live segment has no valno");
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if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
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report("Foreign valno in live segment", MF, LI);
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*OS << *I << " has a bad valno\n";
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if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
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report("Foreign valno in live segment", MF, LR);
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*OS << S << " has a bad valno\n";
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}
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if (VNI->isUnused()) {
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report("Live segment valno is marked unused", MF, LI);
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*OS << *I << '\n';
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report("Live segment valno is marked unused", MF, LR);
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*OS << S << '\n';
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}
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
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if (!MBB) {
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report("Bad start of live segment, no basic block", MF, LI);
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*OS << *I << '\n';
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report("Bad start of live segment, no basic block", MF, LR);
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*OS << S << '\n';
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return;
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}
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SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
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if (I->start != MBBStartIdx && I->start != VNI->def) {
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report("Live segment must begin at MBB entry or valno def", MBB, LI);
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*OS << *I << '\n';
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if (S.start != MBBStartIdx && S.start != VNI->def) {
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report("Live segment must begin at MBB entry or valno def", MBB, LR);
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*OS << S << '\n';
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}
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const MachineBasicBlock *EndMBB =
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LiveInts->getMBBFromIndex(I->end.getPrevSlot());
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LiveInts->getMBBFromIndex(S.end.getPrevSlot());
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if (!EndMBB) {
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report("Bad end of live segment, no basic block", MF, LI);
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*OS << *I << '\n';
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report("Bad end of live segment, no basic block", MF, LR);
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*OS << S << '\n';
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return;
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}
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// No more checks for live-out segments.
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if (I->end == LiveInts->getMBBEndIdx(EndMBB))
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if (S.end == LiveInts->getMBBEndIdx(EndMBB))
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return;
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// RegUnit intervals are allowed dead phis.
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if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
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I->start == VNI->def && I->end == VNI->def.getDeadSlot())
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if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
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S.start == VNI->def && S.end == VNI->def.getDeadSlot())
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return;
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// The live segment is ending inside EndMBB
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const MachineInstr *MI =
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LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
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LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
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if (!MI) {
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report("Live segment doesn't end at a valid instruction", EndMBB, LI);
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*OS << *I << '\n';
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report("Live segment doesn't end at a valid instruction", EndMBB, LR);
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*OS << S << '\n';
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return;
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}
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// The block slot must refer to a basic block boundary.
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if (I->end.isBlock()) {
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report("Live segment ends at B slot of an instruction", EndMBB, LI);
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*OS << *I << '\n';
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if (S.end.isBlock()) {
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report("Live segment ends at B slot of an instruction", EndMBB, LR);
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*OS << S << '\n';
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}
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if (I->end.isDead()) {
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if (S.end.isDead()) {
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// Segment ends on the dead slot.
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// That means there must be a dead def.
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if (!SlotIndex::isSameInstr(I->start, I->end)) {
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report("Live segment ending at dead slot spans instructions", EndMBB, LI);
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*OS << *I << '\n';
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if (!SlotIndex::isSameInstr(S.start, S.end)) {
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report("Live segment ending at dead slot spans instructions", EndMBB, LR);
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*OS << S << '\n';
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}
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}
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// A live segment can only end at an early-clobber slot if it is being
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// redefined by an early-clobber def.
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if (I->end.isEarlyClobber()) {
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if (I+1 == LI.end() || (I+1)->start != I->end) {
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if (S.end.isEarlyClobber()) {
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if (I+1 == LR.end() || (I+1)->start != S.end) {
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report("Live segment ending at early clobber slot must be "
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"redefined by an EC def in the same instruction", EndMBB, LI);
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*OS << *I << '\n';
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"redefined by an EC def in the same instruction", EndMBB, LR);
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*OS << S << '\n';
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}
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}
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// The following checks only apply to virtual registers. Physreg liveness
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// is too weird to check.
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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// A live segment can end with either a redefinition, a kill flag on a
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// use, or a dead flag on a def.
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bool hasRead = false;
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bool hasDeadDef = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || MOI->getReg() != LI.reg)
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if (!MOI->isReg() || MOI->getReg() != Reg)
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continue;
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if (MOI->readsReg())
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hasRead = true;
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@ -1516,15 +1537,15 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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hasDeadDef = true;
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}
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if (I->end.isDead()) {
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if (S.end.isDead()) {
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if (!hasDeadDef) {
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report("Instruction doesn't have a dead def operand", MI);
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*OS << *I << " in " << LI << '\n';
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*OS << S << " in " << LR << '\n';
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}
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} else {
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if (!hasRead) {
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report("Instruction ending live segment doesn't read the register", MI);
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*OS << *I << " in " << LI << '\n';
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*OS << S << " in " << LR << '\n';
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}
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}
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}
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@ -1532,7 +1553,7 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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// Now check all the basic blocks in this live segment.
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MachineFunction::const_iterator MFI = MBB;
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// Is this live segment the beginning of a non-PHIDef VN?
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if (I->start == VNI->def && !VNI->isPHIDef()) {
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if (S.start == VNI->def && !VNI->isPHIDef()) {
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// Not live-in to any blocks.
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if (MBB == EndMBB)
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return;
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@ -1540,9 +1561,9 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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++MFI;
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}
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for (;;) {
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assert(LiveInts->isLiveInToMBB(LI, MFI));
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assert(LiveInts->isLiveInToMBB(LR, MFI));
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// We don't know how to track physregs into a landing pad.
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if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
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if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
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MFI->isLandingPad()) {
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if (&*MFI == EndMBB)
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break;
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@ -1558,11 +1579,11 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
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PE = MFI->pred_end(); PI != PE; ++PI) {
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SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
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const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
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const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
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// All predecessors must have a live-out value.
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if (!PVNI) {
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report("Register not marked live out of predecessor", *PI, LI);
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report("Register not marked live out of predecessor", *PI, LR);
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*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
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<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
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<< PEnd << '\n';
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@ -1571,7 +1592,7 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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// Only PHI-defs can take different predecessor values.
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if (!IsPHI && PVNI != VNI) {
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report("Different value live out of predecessor", *PI, LI);
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report("Different value live out of predecessor", *PI, LR);
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*OS << "Valno #" << PVNI->id << " live out of BB#"
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<< (*PI)->getNumber() << '@' << PEnd
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<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
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@ -1584,13 +1605,17 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
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}
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}
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void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
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for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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I!=E; ++I)
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verifyLiveIntervalValue(LI, *I);
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void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg) {
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for (LiveRange::const_vni_iterator I = LR.vni_begin(), E = LR.vni_end();
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I != E; ++I)
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verifyLiveRangeValue(LR, *I, Reg);
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for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
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verifyLiveIntervalSegment(LI, I);
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for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
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verifyLiveRangeSegment(LR, I, Reg);
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}
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void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
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verifyLiveRange(LI, LI.reg);
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// Check the LI only has one connected component.
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if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
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