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[DAGCombiner] mulhi + 1 never overflow.

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Summary:
This can be used to optimize large multiplications after legalization.

Depends on D29565

Reviewers: mkuper, spatel, RKSimon, zvi, bkramer, aaboud, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury Sechet 2017-03-01 23:44:17 +00:00
parent b424c9db34
commit a50f957a61
2 changed files with 15 additions and 4 deletions
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13
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2775,6 +2775,19 @@ SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind(SDValue N0,
return OFK_Never;
}
// mulhi + 1 never overflow
if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 &&
(~N1Zero & 0x01) == ~N1Zero)
return OFK_Never;
if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) {
APInt N0Zero, N0One;
computeKnownBits(N0, N0Zero, N0One);
if ((~N0Zero & 0x01) == ~N0Zero)
return OFK_Never;
}
return OFK_Sometime;
}

6
test/CodeGen/X86/overflow.ll
View File

@ -50,10 +50,8 @@ define i128 @mulhioverflow(i64 %a, i64 %b, i64 %c) nounwind {
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: mulq %rsi
; X64-NEXT: andl $1, %ecx
; X64-NEXT: addq %rdx, %rcx
; X64-NEXT: sbbq %rdx, %rdx
; X64-NEXT: andl $1, %edx
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: leaq (%rcx,%rdx), %rax
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: retq
%1 = zext i64 %a to i128
%2 = zext i64 %b to i128