mirror of
https://github.com/RPCSX/llvm.git
synced 2025-01-23 20:57:21 +00:00
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
statements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ca6945e5e2
commit
a5a42d9b3c
@ -708,18 +708,32 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
|
|||||||
// Arithmetic Instructions.
|
// Arithmetic Instructions.
|
||||||
//
|
//
|
||||||
|
|
||||||
// Add with carry register
|
// Helper classes to encode the various T1sIt patterns.
|
||||||
let isCommutable = 1, Uses = [CPSR] in
|
class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
|
||||||
def tADC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
|
string opc, string asm, list<dag> pattern>
|
||||||
"adc", "\t$Rdn, $Rm",
|
: T1sIt<oops, iops, itin, opc, asm, pattern>,
|
||||||
[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>,
|
T1DataProcessing<opA> {
|
||||||
T1DataProcessing<0b0101> {
|
|
||||||
// A8.6.2
|
|
||||||
bits<3> Rdn;
|
bits<3> Rdn;
|
||||||
bits<3> Rm;
|
bits<3> Rm;
|
||||||
let Inst{5-3} = Rdn;
|
let Inst{5-3} = Rm;
|
||||||
let Inst{2-0} = Rm;
|
let Inst{2-0} = Rdn;
|
||||||
}
|
}
|
||||||
|
class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
|
||||||
|
string opc, string asm, list<dag> pattern>
|
||||||
|
: T1sIt<oops, iops, itin, opc, asm, pattern>,
|
||||||
|
T1General<opA> {
|
||||||
|
bits<3> Rdn;
|
||||||
|
bits<8> imm8;
|
||||||
|
let Inst{10-8} = Rdn;
|
||||||
|
let Inst{7-0} = imm8;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Add with carry register
|
||||||
|
let isCommutable = 1, Uses = [CPSR] in
|
||||||
|
def tADC : // A8.6.2
|
||||||
|
T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
|
||||||
|
"adc", "\t$Rdn, $Rm",
|
||||||
|
[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
|
|
||||||
// Add immediate
|
// Add immediate
|
||||||
def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
||||||
@ -735,16 +749,11 @@ def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
|||||||
let Inst{2-0} = Rd;
|
let Inst{2-0} = Rd;
|
||||||
}
|
}
|
||||||
|
|
||||||
def tADDi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
|
def tADDi8 : // A8.6.4 T2
|
||||||
"add", "\t$Rdn, $imm8",
|
T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
|
||||||
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
|
IIC_iALUi,
|
||||||
T1General<{1,1,0,?,?}> {
|
"add", "\t$Rdn, $imm8",
|
||||||
// A8.6.4 T2
|
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<8> imm8;
|
|
||||||
let Inst{10-8} = Rdn;
|
|
||||||
let Inst{7-0} = imm8;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Add register
|
// Add register
|
||||||
let isCommutable = 1 in
|
let isCommutable = 1 in
|
||||||
@ -775,16 +784,11 @@ def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
|
|||||||
|
|
||||||
// AND register
|
// AND register
|
||||||
let isCommutable = 1 in
|
let isCommutable = 1 in
|
||||||
def tAND : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
|
def tAND : // A8.6.12
|
||||||
"and", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iBITr,
|
||||||
T1DataProcessing<0b0000> {
|
"and", "\t$Rdn, $Rm",
|
||||||
// A8.6.12
|
[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// ASR immediate
|
// ASR immediate
|
||||||
def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
||||||
@ -801,28 +805,18 @@ def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// ASR register
|
// ASR register
|
||||||
def tASRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
|
def tASRrr : // A8.6.15
|
||||||
"asr", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iMOVsr,
|
||||||
T1DataProcessing<0b0100> {
|
"asr", "\t$Rdn, $Rm",
|
||||||
// A8.6.15
|
[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// BIC register
|
// BIC register
|
||||||
def tBIC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
|
def tBIC : // A8.6.20
|
||||||
"bic", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
|
IIC_iBITr,
|
||||||
T1DataProcessing<0b1110> {
|
"bic", "\t$Rdn, $Rm",
|
||||||
// A8.6.20
|
[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// CMN register
|
// CMN register
|
||||||
let isCompare = 1, Defs = [CPSR] in {
|
let isCompare = 1, Defs = [CPSR] in {
|
||||||
@ -915,16 +909,11 @@ def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
|
|||||||
|
|
||||||
// XOR register
|
// XOR register
|
||||||
let isCommutable = 1 in
|
let isCommutable = 1 in
|
||||||
def tEOR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
|
def tEOR : // A8.6.45
|
||||||
"eor", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iBITr,
|
||||||
T1DataProcessing<0b0001> {
|
"eor", "\t$Rdn, $Rm",
|
||||||
// A8.6.45
|
[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// LSL immediate
|
// LSL immediate
|
||||||
def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
||||||
@ -941,16 +930,11 @@ def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// LSL register
|
// LSL register
|
||||||
def tLSLrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
|
def tLSLrr : // A8.6.89
|
||||||
"lsl", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iMOVsr,
|
||||||
T1DataProcessing<0b0010> {
|
"lsl", "\t$Rdn, $Rm",
|
||||||
// A8.6.89
|
[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// LSR immediate
|
// LSR immediate
|
||||||
def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
||||||
@ -967,16 +951,11 @@ def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
|
|||||||
}
|
}
|
||||||
|
|
||||||
// LSR register
|
// LSR register
|
||||||
def tLSRrr : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
|
def tLSRrr : // A8.6.91
|
||||||
"lsr", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iMOVsr,
|
||||||
T1DataProcessing<0b0011> {
|
"lsr", "\t$Rdn, $Rm",
|
||||||
// A8.6.91
|
[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Move register
|
// Move register
|
||||||
let isMoveImm = 1 in
|
let isMoveImm = 1 in
|
||||||
@ -1018,16 +997,11 @@ def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
|
|||||||
|
|
||||||
// multiply register
|
// multiply register
|
||||||
let isCommutable = 1 in
|
let isCommutable = 1 in
|
||||||
def tMUL : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMUL32,
|
def tMUL : // A8.6.105 T1
|
||||||
"mul", "\t$Rdn, $Rm, $Rdn", /* A8.6.105 MUL Encoding T1 */
|
T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iMUL32,
|
||||||
T1DataProcessing<0b1101> {
|
"mul", "\t$Rdn, $Rm, $Rdn",
|
||||||
// A8.6.105
|
[(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// move inverse register
|
// move inverse register
|
||||||
def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
|
def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
|
||||||
@ -1043,16 +1017,11 @@ def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
|
|||||||
|
|
||||||
// Bitwise or register
|
// Bitwise or register
|
||||||
let isCommutable = 1 in
|
let isCommutable = 1 in
|
||||||
def tORR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iBITr,
|
def tORR : // A8.6.114
|
||||||
"orr", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iBITr,
|
||||||
T1DataProcessing<0b1100> {
|
"orr", "\t$Rdn, $Rm",
|
||||||
// A8.6.114
|
[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Swaps
|
// Swaps
|
||||||
def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
|
def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
|
||||||
@ -1098,19 +1067,14 @@ def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
|
|||||||
let Inst{2-0} = Rd;
|
let Inst{2-0} = Rd;
|
||||||
}
|
}
|
||||||
|
|
||||||
// rotate right register
|
// Rotate right register
|
||||||
def tROR : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iMOVsr,
|
def tROR : // A8.6.139
|
||||||
"ror", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iMOVsr,
|
||||||
T1DataProcessing<0b0111> {
|
"ror", "\t$Rdn, $Rm",
|
||||||
// A8.6.139
|
[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// negate register
|
// Negate register
|
||||||
def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
|
def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
|
||||||
"rsb", "\t$Rd, $Rn, #0",
|
"rsb", "\t$Rd, $Rn, #0",
|
||||||
[(set tGPR:$Rd, (ineg tGPR:$Rn))]>,
|
[(set tGPR:$Rd, (ineg tGPR:$Rn))]>,
|
||||||
@ -1124,16 +1088,11 @@ def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
|
|||||||
|
|
||||||
// Subtract with carry register
|
// Subtract with carry register
|
||||||
let Uses = [CPSR] in
|
let Uses = [CPSR] in
|
||||||
def tSBC : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
|
def tSBC : // A8.6.151
|
||||||
"sbc", "\t$Rdn, $Rm",
|
T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
|
||||||
[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
|
IIC_iALUr,
|
||||||
T1DataProcessing<0b0110> {
|
"sbc", "\t$Rdn, $Rm",
|
||||||
// A8.6.151
|
[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<3> Rm;
|
|
||||||
let Inst{5-3} = Rm;
|
|
||||||
let Inst{2-0} = Rdn;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Subtract immediate
|
// Subtract immediate
|
||||||
def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
||||||
@ -1149,16 +1108,11 @@ def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
|
|||||||
let Inst{2-0} = Rd;
|
let Inst{2-0} = Rd;
|
||||||
}
|
}
|
||||||
|
|
||||||
def tSUBi8 : T1sIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), IIC_iALUi,
|
def tSUBi8 : // A8.6.210 T2
|
||||||
"sub", "\t$Rdn, $imm8",
|
T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
|
||||||
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
|
IIC_iALUi,
|
||||||
T1General<{1,1,1,?,?}> {
|
"sub", "\t$Rdn, $imm8",
|
||||||
// A8.6.210 T2
|
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
|
||||||
bits<3> Rdn;
|
|
||||||
bits<8> imm8;
|
|
||||||
let Inst{10-8} = Rdn;
|
|
||||||
let Inst{7-0} = imm8;
|
|
||||||
}
|
|
||||||
|
|
||||||
// subtract register
|
// subtract register
|
||||||
def tSUBrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
|
def tSUBrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
|
||||||
|
Loading…
x
Reference in New Issue
Block a user