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Allow to truncate left shift with non-constant shift amount
That is pretty common for clang to produce code like (shl %x, (and %amt, 31)). In this situation we can still perform trunc (shl) into shl (trunc) conversion given the known value range of shift amount. Differential Revision: https://reviews.llvm.org/D34723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306499 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stanislav Mekhanoshin
parent
64a075b52c
commit
a5e3faf5db
@ -8210,18 +8210,20 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
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(!LegalOperations || TLI.isOperationLegalOrCustom(ISD::SHL, VT)) &&
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TLI.isTypeDesirableForOp(ISD::SHL, VT)) {
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if (const ConstantSDNode *CAmt = isConstOrConstSplat(N0.getOperand(1))) {
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uint64_t Amt = CAmt->getZExtValue();
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unsigned Size = VT.getScalarSizeInBits();
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SDValue Amt = N0.getOperand(1);
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KnownBits Known;
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DAG.computeKnownBits(Amt, Known);
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unsigned Size = VT.getScalarSizeInBits();
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if (Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size)) {
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SDLoc SL(N);
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EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
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if (Amt < Size) {
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SDLoc SL(N);
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EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
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return DAG.getNode(ISD::SHL, SL, VT, Trunc,
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DAG.getConstant(Amt, SL, AmtVT));
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
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if (AmtVT != Amt.getValueType()) {
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Amt = DAG.getZExtOrTrunc(Amt, SL, AmtVT);
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AddToWorklist(Amt.getNode());
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}
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return DAG.getNode(ISD::SHL, SL, VT, Trunc, Amt);
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}
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}
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@ -16,23 +16,6 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shl_pat:
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; GCN-DAG: s_load_dword s[[SHL:[0-9]+]]
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; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN-DAG: s_sub_i32 s[[SHR:[0-9]+]], 32, s[[SHL]]
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
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define amdgpu_kernel void @alignbit_shl_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_v:
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; GCN-DAG: load_dword v[[SHR:[0-9]+]],
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; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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@ -53,27 +36,6 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shl_pat_v:
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; GCN-DAG: load_dword v[[SHL:[0-9]+]],
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; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN-DAG: v_sub_i32_e32 v[[SHR:[0-9]+]], {{[^,]+}}, 32, v[[SHL]]
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
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define amdgpu_kernel void @alignbit_shl_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
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%tmp = load i64, i64 addrspace(1)* %gep1, align 8
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%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid
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%amt = load i32, i32 addrspace(1)* %gep2, align 4
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%tmp3 = and i32 %amt, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %gep2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and30:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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@ -90,22 +52,6 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shl_pat_wrong_and30:
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; Negative test, wrong constant
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; GCN: v_lshl_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shl_pat_wrong_and30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 30
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and63:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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@ -122,21 +68,6 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shl_pat_wrong_and63:
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; Negative test, wrong constant
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; GCN: v_lshl_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shl_pat_wrong_and63(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 63
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable }
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@ -243,3 +243,77 @@ define amdgpu_kernel void @trunc_shl_31_i32_i64_multi_use(i32 addrspace(1)* %out
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store volatile i64 %shl, i64 addrspace(1)* %in
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_and31:
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; GCN: s_and_b32 s[[AMT:[0-9]+]], s{{[0-9]+}}, 31
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; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, s[[AMT]], v{{[0-9]+}}
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; GCN-NOT: v_lshl_b64
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; GCN-NOT: v_lshlrev_b64
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define amdgpu_kernel void @trunc_shl_and31(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_and30:
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; GCN: s_and_b32 s[[AMT:[0-9]+]], s{{[0-9]+}}, 30
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; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, s[[AMT]], v{{[0-9]+}}
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; GCN-NOT: v_lshl_b64
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; GCN-NOT: v_lshlrev_b64
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define amdgpu_kernel void @trunc_shl_and30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 30
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_wrong_and63:
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; Negative test, wrong constant
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; GCN: v_lshl_b64
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define amdgpu_kernel void @trunc_shl_wrong_and63(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 63
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_no_and:
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; Negative test, shift can be full 64 bit
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; GCN: v_lshl_b64
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define amdgpu_kernel void @trunc_shl_no_and(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp4 = zext i32 %arg2 to i64
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%tmp5 = shl i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_vec_vec:
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; GCN-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}
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; GCN-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
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; GCN-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; GCN-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 6, v{{[0-9]+}}
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; GCN-NOT: v_lshl_b64
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; GCN-NOT: v_lshlrev_b64
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define amdgpu_kernel void @trunc_shl_vec_vec(<4 x i64> addrspace(1)* %arg) {
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bb:
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%v = load <4 x i64>, <4 x i64> addrspace(1)* %arg, align 32
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%shl = shl <4 x i64> %v, <i64 3, i64 4, i64 5, i64 6>
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store <4 x i64> %shl, <4 x i64> addrspace(1)* %arg, align 32
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ret void
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}
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