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Fix some dwarf register numbers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-05-26 19:25:47 +00:00
parent 4f5716ab88
commit a5e62019d7
3 changed files with 3 additions and 3 deletions
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2
lib/Target/MBlaze/MBlazeRegisterInfo.td
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@ -43,7 +43,7 @@ let Namespace = "MBlaze" in {
def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>; def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>;
def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>; def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>;
def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>; def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>;
def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[5]>; def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[4]>;
def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>; def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>;
def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>; def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>;
def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>; def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>;

2
lib/Target/Mips/MipsRegisterInfo.td
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@ -55,7 +55,7 @@ let Namespace = "Mips" in {
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>; def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;

2
lib/Target/PowerPC/PPCRegisterInfo.td
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@ -256,7 +256,7 @@ def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>;
def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
// VRsave register // VRsave register
def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>; def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
// Carry bit. In the architecture this is really bit 0 of the XER register // Carry bit. In the architecture this is really bit 0 of the XER register
// (which really is SPR register 1); this is the only bit interesting to a // (which really is SPR register 1); this is the only bit interesting to a