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[mips][msa] Implement f16 support
The MIPS MSA ASE provides instructions to convert to and from half precision floating point. This patch teaches the MIPS backend to treat f16 as a legal type and how to promote such values to f32 for the usual set of operations. As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during type legalization. Reviewers: zoran.jovanvoic, vkalintiris Differential Revision: https://reviews.llvm.org/D26398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287349 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
0f37c5c43a
commit
a60ff0d03c
@ -3731,6 +3731,56 @@ def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
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def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
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MSA128B, NoItinerary>;
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// Pseudoes used to implement transparent fp16 support.
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let Predicates = [HasMSA] in {
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def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
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[(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> {
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let usesCustomInserter = 1;
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}
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def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
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[(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> {
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let usesCustomInserter = 1;
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}
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def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd),
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(ins MSA128F16:$ws),
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[(set FGR32Opnd:$fd,
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(f32 (fpextend MSA128F16:$ws)))]> {
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let usesCustomInserter = 1;
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}
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def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
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(ins FGR32Opnd:$fs),
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[(set MSA128F16:$wd,
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(f16 (fpround FGR32Opnd:$fs)))]> {
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let usesCustomInserter = 1;
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}
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def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd),
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(ins MSA128F16:$ws),
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[(set FGR64Opnd:$fd,
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(f64 (fpextend MSA128F16:$ws)))]> {
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let usesCustomInserter = 1;
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}
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def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
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(ins FGR64Opnd:$fs),
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[(set MSA128F16:$wd,
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(f16 (fpround FGR64Opnd:$fs)))]> {
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let usesCustomInserter = 1;
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}
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def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
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(TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>;
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def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
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(FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
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(MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
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ISA_MIPS1_NOT_32R6_64R6;
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}
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// Vector extraction with fixed index.
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//
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// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
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@ -400,6 +400,8 @@ def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
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// This class allows us to represent this in codegen patterns.
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def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
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def MSA128F16 : RegisterClass<"Mips", [f16], 128, (sequence "W%u", 0, 31)>;
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def MSA128B: RegisterClass<"Mips", [v16i8], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
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@ -646,6 +648,10 @@ def COP3Opnd : RegisterOperand<COP3> {
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let ParserMatchClass = COP3AsmOperand;
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}
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def MSA128F16Opnd : RegisterOperand<MSA128F16> {
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let ParserMatchClass = MSA128AsmOperand;
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}
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def MSA128BOpnd : RegisterOperand<MSA128B> {
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let ParserMatchClass = MSA128AsmOperand;
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}
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@ -92,6 +92,44 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
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addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
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addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
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// f16 is a storage-only type, always promote it to f32.
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addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
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setOperationAction(ISD::SETCC, MVT::f16, Promote);
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setOperationAction(ISD::BR_CC, MVT::f16, Promote);
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setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
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setOperationAction(ISD::SELECT, MVT::f16, Promote);
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setOperationAction(ISD::FADD, MVT::f16, Promote);
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setOperationAction(ISD::FSUB, MVT::f16, Promote);
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setOperationAction(ISD::FMUL, MVT::f16, Promote);
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setOperationAction(ISD::FDIV, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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setOperationAction(ISD::FMA, MVT::f16, Promote);
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setOperationAction(ISD::FNEG, MVT::f16, Promote);
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setOperationAction(ISD::FABS, MVT::f16, Promote);
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setOperationAction(ISD::FCEIL, MVT::f16, Promote);
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setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::f16, Promote);
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setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
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setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
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setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FRINT, MVT::f16, Promote);
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setOperationAction(ISD::FSIN, MVT::f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
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setOperationAction(ISD::FSQRT, MVT::f16, Promote);
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setOperationAction(ISD::FEXP, MVT::f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::f16, Promote);
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setOperationAction(ISD::FROUND, MVT::f16, Promote);
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setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
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setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
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setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::SRA);
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@ -1172,6 +1210,18 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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return emitFEXP2_W_1(MI, BB);
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case Mips::FEXP2_D_1_PSEUDO:
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return emitFEXP2_D_1(MI, BB);
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case Mips::ST_F16:
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return emitST_F16_PSEUDO(MI, BB);
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case Mips::LD_F16:
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return emitLD_F16_PSEUDO(MI, BB);
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case Mips::MSA_FP_EXTEND_W_PSEUDO:
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return emitFPEXTEND_PSEUDO(MI, BB, false);
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case Mips::MSA_FP_ROUND_W_PSEUDO:
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return emitFPROUND_PSEUDO(MI, BB, false);
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case Mips::MSA_FP_EXTEND_D_PSEUDO:
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return emitFPEXTEND_PSEUDO(MI, BB, true);
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case Mips::MSA_FP_ROUND_D_PSEUDO:
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return emitFPROUND_PSEUDO(MI, BB, true);
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}
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}
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@ -3372,6 +3422,304 @@ MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
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return BB;
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}
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// Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
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// register.
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//
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// STF16 MSA128F16:$wd, mem_simm10:$addr
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// =>
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// copy_u.h $rtemp,$wd[0]
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// sh $rtemp, $addr
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//
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// Safety: We can't use st.h & co as they would over write the memory after
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// the destination. It would require half floats be allocated 16 bytes(!) of
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// space.
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MachineBasicBlock *
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MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Ws = MI.getOperand(0).getReg();
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unsigned Rt = MI.getOperand(1).getReg();
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const MachineMemOperand &MMO = **MI.memoperands_begin();
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unsigned Imm = MMO.getOffset();
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// Caution: A load via the GOT can expand to a GPR32 operand, a load via
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// spill and reload can expand as a GPR64 operand. Examine the
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// operand in detail and default to ABI.
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const TargetRegisterClass *RC =
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MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
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: (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
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: &Mips::GPR64RegClass);
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const bool UsingMips32 = RC == &Mips::GPR32RegClass;
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unsigned Rs = RegInfo.createVirtualRegister(RC);
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
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BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
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.addReg(Rs)
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.addReg(Rt)
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.addImm(Imm)
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.addMemOperand(BB->getParent()->getMachineMemOperand(
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&MMO, MMO.getOffset(), MMO.getSize()));
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MI.eraseFromParent();
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return BB;
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}
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// Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
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//
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// LD_F16 MSA128F16:$wd, mem_simm10:$addr
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// =>
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// lh $rtemp, $addr
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// fill.h $wd, $rtemp
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//
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// Safety: We can't use ld.h & co as they over-read from the source.
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// Additionally, if the address is not modulo 16, 2 cases can occur:
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// a) Segmentation fault as the load instruction reads from a memory page
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// memory it's not supposed to.
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// b) The load crosses an implementation specific boundary, requiring OS
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// intervention.
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//
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MachineBasicBlock *
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MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Wd = MI.getOperand(0).getReg();
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// Caution: A load via the GOT can expand to a GPR32 operand, a load via
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// spill and reload can expand as a GPR64 operand. Examine the
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// operand in detail and default to ABI.
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const TargetRegisterClass *RC =
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MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
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: (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
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: &Mips::GPR64RegClass);
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const bool UsingMips32 = RC == &Mips::GPR32RegClass;
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unsigned Rt = RegInfo.createVirtualRegister(RC);
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
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for (unsigned i = 1; i < MI.getNumOperands(); i++)
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MIB.addOperand(MI.getOperand(i));
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BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
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MI.eraseFromParent();
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return BB;
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}
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// Emit the FPROUND_PSEUDO instruction.
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//
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// Round an FGR64Opnd, FGR32Opnd to an f16.
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//
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// Safety: Cycle the operand through the GPRs so the result always ends up
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// the correct MSA register.
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//
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// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
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// / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
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// (which they can be, as the MSA registers are defined to alias the
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// FPU's 64 bit and 32 bit registers) the result can be accessed using
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// the correct register class. That requires operands be tie-able across
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// register classes which have a sub/super register class relationship.
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//
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// For FPG32Opnd:
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//
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// FPROUND MSA128F16:$wd, FGR32Opnd:$fs
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// =>
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// mfc1 $rtemp, $fs
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// fill.w $rtemp, $wtemp
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// fexdo.w $wd, $wtemp, $wtemp
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//
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// For FPG64Opnd on mips32r2+:
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//
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// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
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// =>
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// mfc1 $rtemp, $fs
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// fill.w $rtemp, $wtemp
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// mfhc1 $rtemp2, $fs
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// insert.w $wtemp[1], $rtemp2
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// insert.w $wtemp[3], $rtemp2
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// fexdo.w $wtemp2, $wtemp, $wtemp
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// fexdo.h $wd, $temp2, $temp2
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//
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// For FGR64Opnd on mips64r2+:
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//
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// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
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// =>
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// dmfc1 $rtemp, $fs
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// fill.d $rtemp, $wtemp
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// fexdo.w $wtemp2, $wtemp, $wtemp
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// fexdo.h $wd, $wtemp2, $wtemp2
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//
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// Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
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// undef bits are "just right" and the exception enable bits are
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// set. By using fill.w to replicate $fs into all elements over
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// insert.w for one element, we avoid that potiential case. If
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// fexdo.[hw] causes an exception in, the exception is valid and it
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// occurs for all elements.
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//
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MachineBasicBlock *
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MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
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MachineBasicBlock *BB,
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bool IsFGR64) const {
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// Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
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// here. It's technically doable to support MIPS32 here, but the ISA forbids
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// it.
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assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
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bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Wd = MI.getOperand(0).getReg();
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unsigned Fs = MI.getOperand(1).getReg();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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const TargetRegisterClass *GPRRC =
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IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
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unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
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// Perform the register class copy as mentioned above.
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unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
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BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
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BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
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unsigned WPHI = Wtemp;
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if (!Subtarget.hasMips64() && IsFGR64) {
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unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
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BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
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unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
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.addReg(Wtemp)
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.addReg(Rtemp2)
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.addImm(1);
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BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
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.addReg(Wtemp2)
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.addReg(Rtemp2)
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.addImm(3);
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WPHI = Wtemp3;
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}
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if (IsFGR64) {
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unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
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.addReg(WPHI)
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.addReg(WPHI);
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WPHI = Wtemp2;
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}
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BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
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MI.eraseFromParent();
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return BB;
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}
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// Emit the FPEXTEND_PSEUDO instruction.
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//
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// Expand an f16 to either a FGR32Opnd or FGR64Opnd.
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//
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// Safety: Cycle the result through the GPRs so the result always ends up
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// the correct floating point register.
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//
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// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
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// / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
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// (which they can be, as the MSA registers are defined to alias the
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// FPU's 64 bit and 32 bit registers) the result can be accessed using
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// the correct register class. That requires operands be tie-able across
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// register classes which have a sub/super register class relationship. I
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// haven't checked.
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//
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// For FGR32Opnd:
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//
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// FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
|
||||
// =>
|
||||
// fexupr.w $wtemp, $ws
|
||||
// copy_s.w $rtemp, $ws[0]
|
||||
// mtc1 $rtemp, $fd
|
||||
//
|
||||
// For FGR64Opnd on Mips64:
|
||||
//
|
||||
// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
|
||||
// =>
|
||||
// fexupr.w $wtemp, $ws
|
||||
// fexupr.d $wtemp2, $wtemp
|
||||
// copy_s.d $rtemp, $wtemp2s[0]
|
||||
// dmtc1 $rtemp, $fd
|
||||
//
|
||||
// For FGR64Opnd on Mips32:
|
||||
//
|
||||
// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
|
||||
// =>
|
||||
// fexupr.w $wtemp, $ws
|
||||
// fexupr.d $wtemp2, $wtemp
|
||||
// copy_s.w $rtemp, $wtemp2[0]
|
||||
// mtc1 $rtemp, $ftemp
|
||||
// copy_s.w $rtemp2, $wtemp2[1]
|
||||
// $fd = mthc1 $rtemp2, $ftemp
|
||||
//
|
||||
MachineBasicBlock *
|
||||
MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB,
|
||||
bool IsFGR64) const {
|
||||
|
||||
// Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
|
||||
// here. It's technically doable to support MIPS32 here, but the ISA forbids
|
||||
// it.
|
||||
assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
|
||||
|
||||
bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
|
||||
bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
|
||||
|
||||
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
unsigned Fd = MI.getOperand(0).getReg();
|
||||
unsigned Ws = MI.getOperand(1).getReg();
|
||||
|
||||
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
|
||||
const TargetRegisterClass *GPRRC =
|
||||
IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
||||
unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
|
||||
unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
|
||||
|
||||
unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
|
||||
unsigned WPHI = Wtemp;
|
||||
|
||||
BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
|
||||
if (IsFGR64) {
|
||||
WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
|
||||
BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
|
||||
}
|
||||
|
||||
// Perform the safety regclass copy mentioned above.
|
||||
unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
|
||||
unsigned FPRPHI = IsFGR64onMips32
|
||||
? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
|
||||
: Fd;
|
||||
BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
|
||||
BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
|
||||
|
||||
if (IsFGR64onMips32) {
|
||||
unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
|
||||
BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
|
||||
.addReg(WPHI)
|
||||
.addImm(1);
|
||||
BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
|
||||
.addReg(FPRPHI)
|
||||
.addReg(Rtemp2);
|
||||
}
|
||||
|
||||
MI.eraseFromParent();
|
||||
return BB;
|
||||
}
|
||||
|
||||
// Emit the FEXP2_W_1 pseudo instructions.
|
||||
//
|
||||
// fexp2_w_1_pseudo $wd, $wt
|
||||
|
||||
@ -111,6 +111,20 @@ namespace llvm {
|
||||
/// \brief Emit the FEXP2_D_1 pseudo instructions.
|
||||
MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
/// \brief Emit the FILL_FW pseudo instruction
|
||||
MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
/// \brief Emit the FILL_FD pseudo instruction
|
||||
MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
/// \brief Emit the FEXP2_W_1 pseudo instructions.
|
||||
MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BB,
|
||||
bool IsFGR64) const;
|
||||
/// \brief Emit the FEXP2_D_1 pseudo instructions.
|
||||
MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
|
||||
MachineBasicBlock *BBi,
|
||||
bool IsFGR64) const;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user