mirror of
https://github.com/RPCSX/llvm.git
synced 2024-11-30 07:00:45 +00:00
ARM: move the builtins libcall CC setup
Move the target specific setup into the target specific lowering setup. As pointed out by Anton, the initial change was moving this too high up the stack resulting in a violation of the layering (the target generic code path setup target specific bits). Sink this into the ARM specific setup. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281088 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool
parent
7deb7e74be
commit
a757788aba
@ -489,173 +489,9 @@ static void InitLibcallNames(const char **Names, const Triple &TT) {
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}
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/// Set default libcall CallingConvs.
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static void InitLibcallCallingConvs(CallingConv::ID *CCs, const Triple &T) {
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static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
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for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
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CCs[LC] = CallingConv::C;
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// The builtins on ARM always use AAPCS, irrespective of wheter C is AAPCS or
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// AAPCS_VFP.
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if (T.getArch() == Triple::arm || T.getArch() == Triple::thumb)
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for (const auto LC : {
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RTLIB::SHL_I16,
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RTLIB::SHL_I32,
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RTLIB::SHL_I64,
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RTLIB::SHL_I128,
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RTLIB::SRL_I16,
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RTLIB::SRL_I32,
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RTLIB::SRL_I64,
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RTLIB::SRL_I128,
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RTLIB::SRA_I16,
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RTLIB::SRA_I32,
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RTLIB::SRA_I64,
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RTLIB::SRA_I128,
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RTLIB::MUL_I8,
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RTLIB::MUL_I16,
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RTLIB::MUL_I32,
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RTLIB::MUL_I64,
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RTLIB::MUL_I128,
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RTLIB::MULO_I32,
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RTLIB::MULO_I64,
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RTLIB::MULO_I128,
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RTLIB::SDIV_I8,
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RTLIB::SDIV_I16,
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RTLIB::SDIV_I32,
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RTLIB::SDIV_I64,
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RTLIB::SDIV_I128,
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RTLIB::UDIV_I8,
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RTLIB::UDIV_I16,
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RTLIB::UDIV_I32,
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RTLIB::UDIV_I64,
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RTLIB::UDIV_I128,
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RTLIB::SREM_I8,
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RTLIB::SREM_I16,
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RTLIB::SREM_I32,
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RTLIB::SREM_I64,
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RTLIB::SREM_I128,
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RTLIB::UREM_I8,
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RTLIB::UREM_I16,
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RTLIB::UREM_I32,
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RTLIB::UREM_I64,
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RTLIB::UREM_I128,
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RTLIB::SDIVREM_I8,
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RTLIB::SDIVREM_I16,
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RTLIB::SDIVREM_I32,
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RTLIB::SDIVREM_I64,
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RTLIB::SDIVREM_I128,
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RTLIB::UDIVREM_I8,
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RTLIB::UDIVREM_I16,
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RTLIB::UDIVREM_I32,
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RTLIB::UDIVREM_I64,
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RTLIB::UDIVREM_I128,
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RTLIB::NEG_I32,
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RTLIB::NEG_I64,
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RTLIB::ADD_F32,
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RTLIB::ADD_F64,
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RTLIB::ADD_F80,
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RTLIB::ADD_F128,
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RTLIB::SUB_F32,
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RTLIB::SUB_F64,
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RTLIB::SUB_F80,
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RTLIB::SUB_F128,
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RTLIB::MUL_F32,
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RTLIB::MUL_F64,
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RTLIB::MUL_F80,
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RTLIB::MUL_F128,
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RTLIB::DIV_F32,
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RTLIB::DIV_F64,
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RTLIB::DIV_F80,
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RTLIB::DIV_F128,
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RTLIB::POWI_F32,
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RTLIB::POWI_F64,
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RTLIB::POWI_F80,
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RTLIB::POWI_F128,
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RTLIB::FPEXT_F64_F128,
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RTLIB::FPEXT_F32_F128,
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RTLIB::FPEXT_F32_F64,
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RTLIB::FPEXT_F16_F32,
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RTLIB::FPROUND_F32_F16,
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RTLIB::FPROUND_F64_F16,
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RTLIB::FPROUND_F80_F16,
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RTLIB::FPROUND_F128_F16,
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RTLIB::FPROUND_F64_F32,
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RTLIB::FPROUND_F80_F32,
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RTLIB::FPROUND_F128_F32,
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RTLIB::FPROUND_F80_F64,
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RTLIB::FPROUND_F128_F64,
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RTLIB::FPTOSINT_F32_I32,
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RTLIB::FPTOSINT_F32_I64,
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RTLIB::FPTOSINT_F32_I128,
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RTLIB::FPTOSINT_F64_I32,
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RTLIB::FPTOSINT_F64_I64,
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RTLIB::FPTOSINT_F64_I128,
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RTLIB::FPTOSINT_F80_I32,
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RTLIB::FPTOSINT_F80_I64,
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RTLIB::FPTOSINT_F80_I128,
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RTLIB::FPTOSINT_F128_I32,
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RTLIB::FPTOSINT_F128_I64,
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RTLIB::FPTOSINT_F128_I128,
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RTLIB::FPTOUINT_F32_I32,
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RTLIB::FPTOUINT_F32_I64,
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RTLIB::FPTOUINT_F32_I128,
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RTLIB::FPTOUINT_F64_I32,
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RTLIB::FPTOUINT_F64_I64,
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RTLIB::FPTOUINT_F64_I128,
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RTLIB::FPTOUINT_F80_I32,
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RTLIB::FPTOUINT_F80_I64,
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RTLIB::FPTOUINT_F80_I128,
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RTLIB::FPTOUINT_F128_I32,
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RTLIB::FPTOUINT_F128_I64,
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RTLIB::FPTOUINT_F128_I128,
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RTLIB::SINTTOFP_I32_F32,
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RTLIB::SINTTOFP_I32_F64,
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RTLIB::SINTTOFP_I32_F80,
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RTLIB::SINTTOFP_I32_F128,
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RTLIB::SINTTOFP_I64_F32,
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RTLIB::SINTTOFP_I64_F64,
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RTLIB::SINTTOFP_I64_F80,
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RTLIB::SINTTOFP_I64_F128,
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RTLIB::SINTTOFP_I128_F32,
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RTLIB::SINTTOFP_I128_F64,
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RTLIB::SINTTOFP_I128_F80,
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RTLIB::SINTTOFP_I128_F128,
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RTLIB::UINTTOFP_I32_F32,
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RTLIB::UINTTOFP_I32_F64,
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RTLIB::UINTTOFP_I32_F80,
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RTLIB::UINTTOFP_I32_F128,
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RTLIB::UINTTOFP_I64_F32,
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RTLIB::UINTTOFP_I64_F64,
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RTLIB::UINTTOFP_I64_F80,
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RTLIB::UINTTOFP_I64_F128,
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RTLIB::UINTTOFP_I128_F32,
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RTLIB::UINTTOFP_I128_F64,
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RTLIB::UINTTOFP_I128_F80,
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RTLIB::UINTTOFP_I128_F128,
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RTLIB::OEQ_F32,
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RTLIB::OEQ_F64,
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RTLIB::OEQ_F128,
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RTLIB::UNE_F32,
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RTLIB::UNE_F64,
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RTLIB::UNE_F128,
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RTLIB::OGE_F32,
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RTLIB::OGE_F64,
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RTLIB::OGE_F128,
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RTLIB::OLT_F32,
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RTLIB::OLT_F64,
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RTLIB::OLT_F128,
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RTLIB::OLE_F32,
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RTLIB::OLE_F64,
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RTLIB::OLE_F128,
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RTLIB::OGT_F32,
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RTLIB::OGT_F64,
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RTLIB::OGT_F128,
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RTLIB::UO_F32,
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RTLIB::UO_F64,
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RTLIB::UO_F128,
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RTLIB::O_F32,
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RTLIB::O_F64,
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RTLIB::O_F128,
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})
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CCs[LC] = CallingConv::ARM_AAPCS;
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}
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/// getFPEXT - Return the FPEXT_*_* value for the given types, or
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@ -997,7 +833,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
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InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
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InitCmpLibcallCCs(CmpLibcallCCs);
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InitLibcallCallingConvs(LibcallCallingConvs, TM.getTargetTriple());
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InitLibcallCallingConvs(LibcallCallingConvs);
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}
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void TargetLoweringBase::initActions() {
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@ -80,6 +80,171 @@ namespace {
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};
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}
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void ARMTargetLowering::InitLibcallCallingConvs() {
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// The builtins on ARM always use AAPCS, irrespective of wheter C is AAPCS or
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// AAPCS_VFP.
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for (const auto LC : {
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RTLIB::SHL_I16,
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RTLIB::SHL_I32,
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RTLIB::SHL_I64,
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RTLIB::SHL_I128,
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RTLIB::SRL_I16,
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RTLIB::SRL_I32,
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RTLIB::SRL_I64,
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RTLIB::SRL_I128,
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RTLIB::SRA_I16,
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RTLIB::SRA_I32,
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RTLIB::SRA_I64,
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RTLIB::SRA_I128,
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RTLIB::MUL_I8,
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RTLIB::MUL_I16,
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RTLIB::MUL_I32,
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RTLIB::MUL_I64,
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RTLIB::MUL_I128,
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RTLIB::MULO_I32,
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RTLIB::MULO_I64,
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RTLIB::MULO_I128,
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RTLIB::SDIV_I8,
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RTLIB::SDIV_I16,
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RTLIB::SDIV_I32,
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RTLIB::SDIV_I64,
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RTLIB::SDIV_I128,
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RTLIB::UDIV_I8,
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RTLIB::UDIV_I16,
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RTLIB::UDIV_I32,
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RTLIB::UDIV_I64,
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RTLIB::UDIV_I128,
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RTLIB::SREM_I8,
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RTLIB::SREM_I16,
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RTLIB::SREM_I32,
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RTLIB::SREM_I64,
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RTLIB::SREM_I128,
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RTLIB::UREM_I8,
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RTLIB::UREM_I16,
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RTLIB::UREM_I32,
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RTLIB::UREM_I64,
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RTLIB::UREM_I128,
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RTLIB::SDIVREM_I8,
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RTLIB::SDIVREM_I16,
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RTLIB::SDIVREM_I32,
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RTLIB::SDIVREM_I64,
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RTLIB::SDIVREM_I128,
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RTLIB::UDIVREM_I8,
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RTLIB::UDIVREM_I16,
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RTLIB::UDIVREM_I32,
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RTLIB::UDIVREM_I64,
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RTLIB::UDIVREM_I128,
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RTLIB::NEG_I32,
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RTLIB::NEG_I64,
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RTLIB::ADD_F32,
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RTLIB::ADD_F64,
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RTLIB::ADD_F80,
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RTLIB::ADD_F128,
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RTLIB::SUB_F32,
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RTLIB::SUB_F64,
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RTLIB::SUB_F80,
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RTLIB::SUB_F128,
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RTLIB::MUL_F32,
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RTLIB::MUL_F64,
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RTLIB::MUL_F80,
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RTLIB::MUL_F128,
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RTLIB::DIV_F32,
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RTLIB::DIV_F64,
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RTLIB::DIV_F80,
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RTLIB::DIV_F128,
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RTLIB::POWI_F32,
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RTLIB::POWI_F64,
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RTLIB::POWI_F80,
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RTLIB::POWI_F128,
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RTLIB::FPEXT_F64_F128,
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RTLIB::FPEXT_F32_F128,
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RTLIB::FPEXT_F32_F64,
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RTLIB::FPEXT_F16_F32,
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RTLIB::FPROUND_F32_F16,
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RTLIB::FPROUND_F64_F16,
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RTLIB::FPROUND_F80_F16,
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RTLIB::FPROUND_F128_F16,
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RTLIB::FPROUND_F64_F32,
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RTLIB::FPROUND_F80_F32,
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RTLIB::FPROUND_F128_F32,
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RTLIB::FPROUND_F80_F64,
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RTLIB::FPROUND_F128_F64,
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RTLIB::FPTOSINT_F32_I32,
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RTLIB::FPTOSINT_F32_I64,
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RTLIB::FPTOSINT_F32_I128,
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RTLIB::FPTOSINT_F64_I32,
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RTLIB::FPTOSINT_F64_I64,
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RTLIB::FPTOSINT_F64_I128,
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RTLIB::FPTOSINT_F80_I32,
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RTLIB::FPTOSINT_F80_I64,
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RTLIB::FPTOSINT_F80_I128,
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RTLIB::FPTOSINT_F128_I32,
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RTLIB::FPTOSINT_F128_I64,
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RTLIB::FPTOSINT_F128_I128,
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RTLIB::FPTOUINT_F32_I32,
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RTLIB::FPTOUINT_F32_I64,
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RTLIB::FPTOUINT_F32_I128,
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RTLIB::FPTOUINT_F64_I32,
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RTLIB::FPTOUINT_F64_I64,
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RTLIB::FPTOUINT_F64_I128,
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RTLIB::FPTOUINT_F80_I32,
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RTLIB::FPTOUINT_F80_I64,
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RTLIB::FPTOUINT_F80_I128,
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RTLIB::FPTOUINT_F128_I32,
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RTLIB::FPTOUINT_F128_I64,
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RTLIB::FPTOUINT_F128_I128,
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RTLIB::SINTTOFP_I32_F32,
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RTLIB::SINTTOFP_I32_F64,
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RTLIB::SINTTOFP_I32_F80,
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RTLIB::SINTTOFP_I32_F128,
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RTLIB::SINTTOFP_I64_F32,
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RTLIB::SINTTOFP_I64_F64,
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RTLIB::SINTTOFP_I64_F80,
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RTLIB::SINTTOFP_I64_F128,
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RTLIB::SINTTOFP_I128_F32,
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RTLIB::SINTTOFP_I128_F64,
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RTLIB::SINTTOFP_I128_F80,
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RTLIB::SINTTOFP_I128_F128,
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RTLIB::UINTTOFP_I32_F32,
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RTLIB::UINTTOFP_I32_F64,
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RTLIB::UINTTOFP_I32_F80,
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RTLIB::UINTTOFP_I32_F128,
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RTLIB::UINTTOFP_I64_F32,
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RTLIB::UINTTOFP_I64_F64,
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RTLIB::UINTTOFP_I64_F80,
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RTLIB::UINTTOFP_I64_F128,
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RTLIB::UINTTOFP_I128_F32,
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RTLIB::UINTTOFP_I128_F64,
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RTLIB::UINTTOFP_I128_F80,
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RTLIB::UINTTOFP_I128_F128,
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RTLIB::OEQ_F32,
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RTLIB::OEQ_F64,
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RTLIB::OEQ_F128,
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RTLIB::UNE_F32,
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RTLIB::UNE_F64,
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RTLIB::UNE_F128,
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RTLIB::OGE_F32,
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RTLIB::OGE_F64,
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RTLIB::OGE_F128,
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RTLIB::OLT_F32,
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RTLIB::OLT_F64,
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RTLIB::OLT_F128,
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RTLIB::OLE_F32,
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RTLIB::OLE_F64,
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RTLIB::OLE_F128,
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RTLIB::OGT_F32,
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RTLIB::OGT_F64,
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RTLIB::OGT_F128,
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RTLIB::UO_F32,
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RTLIB::UO_F64,
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RTLIB::UO_F128,
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RTLIB::O_F32,
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RTLIB::O_F64,
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RTLIB::O_F128,
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})
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setLibcallCallingConv(LC, CallingConv::ARM_AAPCS);
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}
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// The APCS parameter registers.
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static const MCPhysReg GPRArgRegs[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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@ -167,6 +332,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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InitLibcallCallingConvs();
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if (Subtarget->isTargetMachO()) {
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// Uses VFP for Thumb libfuncs if available.
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if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
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@ -506,6 +506,8 @@ namespace llvm {
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bool HasStandaloneRem = true;
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void InitLibcallCallingConvs();
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void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
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void addDRTypeForNEON(MVT VT);
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void addQRTypeForNEON(MVT VT);
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