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The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wesley Peck 2010-12-12 22:02:31 +00:00
parent d713acb631
commit a7c7b9dccb
9 changed files with 100 additions and 99 deletions
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101
cmake/modules/LLVMLibDeps.cmake
View File

@ -1,67 +1,68 @@
set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa)
set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsCodeGen LLVMMipsInfo LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsCodeGen LLVMMipsInfo LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreInfo)
set(MSVC_LIB_DEPS_LLVMMCJIT LLVMExecutionEngine LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMCJIT LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMObject LLVMSupport) set(MSVC_LIB_DEPS_LLVMObject LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMSupport ) set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZInfo LLVMTarget) set(MSVC_LIB_DEPS_LLVMSystem )
set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMSystemZInfo LLVMTarget)
set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa) set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMipa)
set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86AsmPrinter LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMXCoreInfo)
set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa)

2
lib/Target/MBlaze/MBlazeAsmBackend.cpp
View File

@ -61,7 +61,7 @@ public:
static unsigned getRelaxedOpcode(unsigned Op) { static unsigned getRelaxedOpcode(unsigned Op) {
switch (Op) { switch (Op) {
default: return Op; default: return Op;
case MBlaze::ADDI: return MBlaze::ADDI32; case MBlaze::ADDIK: return MBlaze::ADDIK32;
case MBlaze::ORI: return MBlaze::ORI32; case MBlaze::ORI: return MBlaze::ORI32;
case MBlaze::BRLID: return MBlaze::BRLID32; case MBlaze::BRLID: return MBlaze::BRLID32;
} }

4
lib/Target/MBlaze/MBlazeFrameInfo.cpp
View File

@ -187,7 +187,7 @@ void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const {
int RAOffset = MBlazeFI->getRAStackOffset(); int RAOffset = MBlazeFI->getRAStackOffset();
// Adjust stack : addi R1, R1, -imm // Adjust stack : addi R1, R1, -imm
BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDI), MBlaze::R1) BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDIK), MBlaze::R1)
.addReg(MBlaze::R1).addImm(-StackSize); .addReg(MBlaze::R1).addImm(-StackSize);
// swi R15, R1, stack_loc // swi R15, R1, stack_loc
@ -242,7 +242,7 @@ void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF,
// addi R1, R1, imm // addi R1, R1, imm
if (StackSize) { if (StackSize) {
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1) BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDIK), MBlaze::R1)
.addReg(MBlaze::R1).addImm(StackSize); .addReg(MBlaze::R1).addImm(StackSize);
} }
} }

2
lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
View File

@ -210,7 +210,7 @@ SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) {
int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex(); int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex();
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
unsigned Opc = MBlaze::ADDI; unsigned Opc = MBlaze::ADDIK;
if (Node->hasOneUse()) if (Node->hasOneUse())
return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm); return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm); return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);

4
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -268,7 +268,7 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
.addImm(31); .addImm(31);
unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass); unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL) BuildMI(BB, dl, TII->get(MBlaze::ADDIK), IVAL)
.addReg(MI->getOperand(1).getReg()) .addReg(MI->getOperand(1).getReg())
.addImm(0); .addImm(0);
@ -297,7 +297,7 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
else else
llvm_unreachable("Cannot lower unknown shift instruction"); llvm_unreachable("Cannot lower unknown shift instruction");
BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT) BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
.addReg(SAMT) .addReg(SAMT)
.addImm(-1); .addImm(-1);

42
lib/Target/MBlaze/MBlazeInstrFPU.td
View File

@ -143,74 +143,74 @@ let Predicates=[HasFPU] in {
// SET_CC operations // SET_CC operations
let Predicates=[HasFPU] in { let Predicates=[HasFPU] in {
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>; (FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 1)>; (FCMP_EQ GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_EQ GPR:$L, GPR:$R), 2)>; (FCMP_EQ GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(XOR (FCMP_UN GPR:$L, GPR:$R), (XOR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>; (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>; (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>; (FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>; (FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>; (FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>; (FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GT GPR:$L, GPR:$R), 2)>; (FCMP_GT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LT GPR:$L, GPR:$R), 2)>; (FCMP_LT GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_GE GPR:$L, GPR:$R), 2)>; (FCMP_GE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_LE GPR:$L, GPR:$R), 2)>; (FCMP_LE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_EQ GPR:$L, GPR:$R)), 2)>; (FCMP_EQ GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_NE GPR:$L, GPR:$R), 2)>; (FCMP_NE GPR:$L, GPR:$R), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GT GPR:$L, GPR:$R)), 2)>; (FCMP_GT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LT GPR:$L, GPR:$R)), 2)>; (FCMP_LT GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_GE GPR:$L, GPR:$R)), 2)>; (FCMP_GE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(OR (FCMP_UN GPR:$L, GPR:$R), (OR (FCMP_UN GPR:$L, GPR:$R),
(FCMP_LE GPR:$L, GPR:$R)), 2)>; (FCMP_LE GPR:$L, GPR:$R)), 2)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 1)>; (FCMP_UN GPR:$L, GPR:$R), 1)>;
def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO), def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(FCMP_UN GPR:$L, GPR:$R), 2)>; (FCMP_UN GPR:$L, GPR:$R), 2)>;
} }

36
lib/Target/MBlaze/MBlazeInstrInfo.td
View File

@ -327,9 +327,9 @@ class BranchCI<bits<6> op, bits<5> br, string instr_asm> :
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCommutable = 1, isAsCheapAsAMove = 1 in { let isCommutable = 1, isAsCheapAsAMove = 1 in {
def ADD : Arith<0x00, 0x000, "add ", add, IIAlu>; def ADD : Arith<0x00, 0x000, "add ", addc, IIAlu>;
def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>; def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
def ADDK : Arith<0x04, 0x000, "addk ", addc, IIAlu>; def ADDK : Arith<0x04, 0x000, "addk ", add, IIAlu>;
def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>; def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
def AND : Logic<0x21, 0x000, "and ", and>; def AND : Logic<0x21, 0x000, "and ", and>;
def OR : Logic<0x20, 0x000, "or ", or>; def OR : Logic<0x20, 0x000, "or ", or>;
@ -343,9 +343,9 @@ let isAsCheapAsAMove = 1 in {
def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>; def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>; def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>; def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
def RSUB : ArithR<0x01, 0x000, "rsub ", sub, IIAlu>; def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIAlu>;
def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>; def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
def RSUBK : ArithR<0x05, 0x000, "rsubk ", subc, IIAlu>; def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIAlu>;
def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>; def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
} }
@ -589,7 +589,7 @@ let rb = 0 in {
} }
let isCodeGenOnly=1 in { let isCodeGenOnly=1 in {
def ADDI32 : ArithI32<0x08, "addi ", simm16, immSExt16>; def ADDIK32 : ArithI32<0x08, "addik ", simm16, immSExt16>;
def ORI32 : LogicI32<0x28, "ori ">; def ORI32 : LogicI32<0x28, "ori ">;
def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">; def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">;
} }
@ -632,11 +632,11 @@ def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
// Small immediates // Small immediates
def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>; def : Pat<(i32 0), (ADD (i32 R0), (i32 R0))>;
def : Pat<(i32 immSExt16:$imm), (ADDI (i32 R0), imm:$imm)>; def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>;
def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>; def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
// Arbitrary immediates // Arbitrary immediates
def : Pat<(i32 imm:$imm), (ADDI (i32 R0), imm:$imm)>; def : Pat<(i32 imm:$imm), (ADDIK (i32 R0), imm:$imm)>;
// In register sign extension // In register sign extension
def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>; def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>;
@ -659,34 +659,34 @@ def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>;
// SET_CC operations // SET_CC operations
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 1)>; (CMP GPR:$R, GPR:$L), 1)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 2)>; (CMP GPR:$R, GPR:$L), 2)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 3)>; (CMP GPR:$R, GPR:$L), 3)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 4)>; (CMP GPR:$R, GPR:$L), 4)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 5)>; (CMP GPR:$R, GPR:$L), 5)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMP GPR:$R, GPR:$L), 6)>; (CMP GPR:$R, GPR:$L), 6)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 3)>; (CMPU GPR:$R, GPR:$L), 3)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 4)>; (CMPU GPR:$R, GPR:$L), 4)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 5)>; (CMPU GPR:$R, GPR:$L), 5)>;
def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0), (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0),
(CMPU GPR:$R, GPR:$L), 6)>; (CMPU GPR:$R, GPR:$L), 6)>;
// SELECT operations // SELECT operations
@ -765,7 +765,7 @@ def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>; def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>;
// Arithmetic with immediates // Arithmetic with immediates
def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDI GPR:$in, imm:$imm)>; def : Pat<(add (i32 GPR:$in), imm:$imm),(ADDIK GPR:$in, imm:$imm)>;
def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>; def : Pat<(or (i32 GPR:$in), imm:$imm),(ORI GPR:$in, imm:$imm)>;
def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>; def : Pat<(xor (i32 GPR:$in), imm:$imm),(XORI GPR:$in, imm:$imm)>;

4
lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
View File

@ -141,7 +141,7 @@ EmitIMM(const MCInst &MI, unsigned &CurByte,raw_ostream &OS) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: break; default: break;
case MBlaze::ADDI32: case MBlaze::ADDIK32:
case MBlaze::ORI32: case MBlaze::ORI32:
case MBlaze::BRLID32: case MBlaze::BRLID32:
EmitByte(0x0D, CurByte, OS); EmitByte(0x0D, CurByte, OS);
@ -168,7 +168,7 @@ EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel, unsigned &CurByte,
Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind)); Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
break; break;
case MBlaze::ORI32: case MBlaze::ORI32:
case MBlaze::ADDI32: case MBlaze::ADDIK32:
case MBlaze::BRLID32: case MBlaze::BRLID32:
FixupKind = pcrel ? FK_PCRel_4 : FK_Data_4; FixupKind = pcrel ? FK_PCRel_4 : FK_Data_4;
Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind)); Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));

4
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -185,11 +185,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New; MachineInstr *New;
if (Old->getOpcode() == MBlaze::ADJCALLSTACKDOWN) { if (Old->getOpcode() == MBlaze::ADJCALLSTACKDOWN) {
New = BuildMI(MF, Old->getDebugLoc(), TII.get(MBlaze::ADDI), MBlaze::R1) New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
.addReg(MBlaze::R1).addImm(-Amount); .addReg(MBlaze::R1).addImm(-Amount);
} else { } else {
assert(Old->getOpcode() == MBlaze::ADJCALLSTACKUP); assert(Old->getOpcode() == MBlaze::ADJCALLSTACKUP);
New = BuildMI(MF, Old->getDebugLoc(), TII.get(MBlaze::ADDI), MBlaze::R1) New = BuildMI(MF,Old->getDebugLoc(),TII.get(MBlaze::ADDIK),MBlaze::R1)
.addReg(MBlaze::R1).addImm(Amount); .addReg(MBlaze::R1).addImm(Amount);
} }