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add support FNEG and FABS

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-04-02 05:18:38 +00:00
parent b9fccc4193
commit a7ee8b8f04
2 changed files with 19 additions and 5 deletions
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20
lib/Target/IA64/IA64ISelPattern.cpp
View File

@ -80,10 +80,6 @@ namespace {
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
computeRegisterProperties();
addLegalFPImmediate(+0.0);
@ -794,7 +790,21 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
case ISD::FABS: {
Tmp1 = SelectExpr(N.getOperand(0));
assert(DestType == MVT::f64 && "trying to fabs something other than f64?");
BuildMI(BB, IA64::FABS, 1, Result).addReg(Tmp1);
return Result;
}
case ISD::FNEG: {
Tmp1 = SelectExpr(N.getOperand(0));
assert(DestType == MVT::f64 && "trying to fneg something other than f64?");
BuildMI(BB, IA64::FNEG, 1, Result).addReg(Tmp1);
return Result;
}
case ISD::AND: {
switch (N.getValueType()) {
default: assert(0 && "Cannot AND this type!");

4
lib/Target/IA64/IA64InstrInfo.td
View File

@ -227,6 +227,10 @@ def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
"fma $dst = $src1, $src2, $src3;;">;
def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
"fnma $dst = $src1, $src2, $src3;;">;
def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
"fabs $dst = $src;;">;
def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
"fneg $dst = $src;;">;
def CFMAS1 : AForm<0x03, 0x0b,
(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),