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[SystemZ] Add optional argument to some vector string instructions
The vfee[bhf], vfene[bhf], and vistr[bhf] assembler mnemonics are documented in the Principles of Operation to have an optional last operand to encode arbitrary values in a mask field. This commit adds support for those optional operands, and cleans up the patterns to generate vector string instruction as bit. No change to code generation intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284585 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
7b63453e9a
commit
a91221aaa6
@ -1770,15 +1770,25 @@ class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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let M5 = m5;
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}
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multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc, TypedReg tr1,
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TypedReg tr2, bits<4> type, bits<4> modifier = 0,
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bits<4> modifier_cc = 1> {
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def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
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// Declare a pair of instructions, one which sets CC and one which doesn't.
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// The CC-setting form ends with "S" and sets the low bit of M5.
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// The form that does not set CC has an extra operand to optionally allow
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// specifying arbitrary M5 values in assembler.
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multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc,
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TypedReg tr1, TypedReg tr2, bits<4> type> {
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let M3 = type, M4 = 0 in
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def "" : InstVRRa<opcode, (outs tr1.op:$V1),
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(ins tr2.op:$V2, imm32zx4:$M5),
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mnemonic#"\t$V1, $V2, $M5", []>;
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def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
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(!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
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def : InstAlias<mnemonic#"\t$V1, $V2",
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(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
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let Defs = [CC] in
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def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
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modifier_cc>;
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def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
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type, 0, 1>;
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}
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class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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@ -2053,12 +2063,33 @@ class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc, TypedReg tr1,
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TypedReg tr2, bits<4> type,
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bits<4> modifier = 0, bits<4> modifier_cc = 1> {
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def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
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TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
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def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
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!and (modifier, 14)>;
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let Defs = [CC] in
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def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
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modifier_cc>;
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!add (!and (modifier, 14), 1)>;
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}
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// Declare a pair of instructions, one which sets CC and one which doesn't.
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// The CC-setting form ends with "S" and sets the low bit of M5.
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// The form that does not set CC has an extra operand to optionally allow
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// specifying arbitrary M5 values in assembler.
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multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc,
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TypedReg tr1, TypedReg tr2, bits<4> type> {
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let M4 = type in
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def "" : InstVRRb<opcode, (outs tr1.op:$V1),
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(ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
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mnemonic#"\t$V1, $V2, $V3, $M5", []>;
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def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
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(!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
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def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
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(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
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tr2.op:$V3, 0)>;
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let Defs = [CC] in
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def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
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}
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class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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@ -2073,15 +2104,18 @@ class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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let M6 = m6;
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}
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// Declare a pair of instructions, one which sets CC and one which doesn't.
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// The CC-setting form ends with "S" and sets the low bit of M5.
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multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc, TypedReg tr1,
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TypedReg tr2, bits<4> type, bits<4> m5,
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bits<4> modifier = 0, bits<4> modifier_cc = 1> {
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def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
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bits<4> modifier = 0> {
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def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
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m5, !and (modifier, 14)>;
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let Defs = [CC] in
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def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
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m5, modifier_cc>;
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m5, !add (!and (modifier, 14), 1)>;
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}
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class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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@ -2412,18 +2446,22 @@ class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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let M4 = type;
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}
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multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc, TypedReg tr1,
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TypedReg tr2, bits<4> type, bits<4> m5or> {
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// Declare a pair of instructions, one which sets CC and one which doesn't.
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// The CC-setting form ends with "S" and sets the low bit of M5.
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// Also create aliases to make use of M5 operand optional in assembler.
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multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc,
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TypedReg tr1, TypedReg tr2, bits<4> type,
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bits<4> modifier = 0> {
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def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
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imm32zx4even, !and (m5or, 14)>;
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imm32zx4even, !and (modifier, 14)>;
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def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
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(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
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tr2.op:$V3, 0)>;
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let Defs = [CC] in
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def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
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imm32zx4even, !add(!and (m5or, 14), 1)>;
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imm32zx4even, !add(!and (modifier, 14), 1)>;
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def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
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(!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
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tr2.op:$V3, 0)>;
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@ -2531,18 +2569,22 @@ class QuaternaryVRRd<string mnemonic, bits<16> opcode,
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let M5 = type;
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}
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multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc, TypedReg tr1,
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TypedReg tr2, bits<4> type, bits<4> m6or> {
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// Declare a pair of instructions, one which sets CC and one which doesn't.
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// The CC-setting form ends with "S" and sets the low bit of M6.
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// Also create aliases to make use of M6 operand optional in assembler.
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multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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SDPatternOperator operator_cc,
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TypedReg tr1, TypedReg tr2, bits<4> type,
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bits<4> modifier = 0> {
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def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
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imm32zx4even, !and (m6or, 14)>;
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imm32zx4even, !and (modifier, 14)>;
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def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
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(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
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tr2.op:$V3, tr2.op:$V4, 0)>;
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let Defs = [CC] in
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def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
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imm32zx4even, !add (!and (m6or, 14), 1)>;
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imm32zx4even, !add (!and (modifier, 14), 1)>;
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def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
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(!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
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tr2.op:$V3, tr2.op:$V4, 0)>;
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@ -1036,62 +1036,62 @@ let AddedComplexity = 4 in {
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//===----------------------------------------------------------------------===//
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let Predicates = [FeatureVector] in {
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defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, z_vfae_cc,
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v128b, v128b, 0, 0>;
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defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, z_vfae_cc,
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v128h, v128h, 1, 0>;
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defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, z_vfae_cc,
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v128f, v128f, 2, 0>;
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defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, z_vfaez_cc,
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v128b, v128b, 0, 2>;
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defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, z_vfaez_cc,
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v128h, v128h, 1, 2>;
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defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, z_vfaez_cc,
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v128f, v128f, 2, 2>;
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defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb,
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z_vfae_cc, v128b, v128b, 0>;
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defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh,
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z_vfae_cc, v128h, v128h, 1>;
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defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef,
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z_vfae_cc, v128f, v128f, 2>;
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defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb,
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z_vfaez_cc, v128b, v128b, 0, 2>;
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defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh,
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z_vfaez_cc, v128h, v128h, 1, 2>;
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defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf,
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z_vfaez_cc, v128f, v128f, 2, 2>;
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defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, z_vfee_cc,
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v128b, v128b, 0, 0, 1>;
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defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, z_vfee_cc,
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v128h, v128h, 1, 0, 1>;
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defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, z_vfee_cc,
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v128f, v128f, 2, 0, 1>;
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defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, z_vfeez_cc,
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v128b, v128b, 0, 2, 3>;
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defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, z_vfeez_cc,
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v128h, v128h, 1, 2, 3>;
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defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, z_vfeez_cc,
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v128f, v128f, 2, 2, 3>;
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defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb,
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z_vfee_cc, v128b, v128b, 0>;
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defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh,
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z_vfee_cc, v128h, v128h, 1>;
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defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef,
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z_vfee_cc, v128f, v128f, 2>;
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defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb,
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z_vfeez_cc, v128b, v128b, 0, 2>;
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defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh,
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z_vfeez_cc, v128h, v128h, 1, 2>;
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defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf,
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z_vfeez_cc, v128f, v128f, 2, 2>;
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defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, z_vfene_cc,
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v128b, v128b, 0, 0, 1>;
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defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, z_vfene_cc,
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v128h, v128h, 1, 0, 1>;
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defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, z_vfene_cc,
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v128f, v128f, 2, 0, 1>;
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defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb,
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z_vfene_cc, v128b, v128b, 0>;
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defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh,
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z_vfene_cc, v128h, v128h, 1>;
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defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef,
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z_vfene_cc, v128f, v128f, 2>;
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defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb,
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z_vfenez_cc, v128b, v128b, 0, 2, 3>;
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z_vfenez_cc, v128b, v128b, 0, 2>;
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defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh,
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z_vfenez_cc, v128h, v128h, 1, 2, 3>;
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z_vfenez_cc, v128h, v128h, 1, 2>;
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defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf,
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z_vfenez_cc, v128f, v128f, 2, 2, 3>;
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z_vfenez_cc, v128f, v128f, 2, 2>;
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defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, z_vistr_cc,
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v128b, v128b, 0>;
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defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, z_vistr_cc,
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v128h, v128h, 1>;
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defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, z_vistr_cc,
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v128f, v128f, 2>;
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defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb,
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z_vistr_cc, v128b, v128b, 0>;
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defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh,
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z_vistr_cc, v128h, v128h, 1>;
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defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf,
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z_vistr_cc, v128f, v128f, 2>;
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defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb,
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z_vstrc_cc, v128b, v128b, 0, 0>;
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defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch,
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z_vstrc_cc, v128h, v128h, 1, 0>;
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defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf,
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z_vstrc_cc, v128f, v128f, 2, 0>;
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defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb,
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z_vstrcz_cc, v128b, v128b, 0, 2>;
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defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh,
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z_vstrcz_cc, v128h, v128h, 1, 2>;
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defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf,
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z_vstrcz_cc, v128f, v128f, 2, 2>;
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defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb,
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z_vstrc_cc, v128b, v128b, 0>;
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defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch,
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z_vstrc_cc, v128h, v128h, 1>;
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defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf,
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z_vstrc_cc, v128f, v128f, 2>;
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defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb,
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z_vstrcz_cc, v128b, v128b, 0, 2>;
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defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh,
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z_vstrcz_cc, v128h, v128h, 1, 2>;
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defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf,
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z_vstrcz_cc, v128f, v128f, 2, 2>;
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}
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@ -983,10 +983,13 @@
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#CHECK: vfddb %v31, %v31, %v31
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0xe7 0xff 0xf0 0x00 0x3e 0xe5
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#CHECK: vfeeb %v0, %v0, %v0
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#CHECK: vfeeb %v0, %v0, %v0, 0
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0xe7 0x00 0x00 0x00 0x00 0x80
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#CHECK: vfeeb %v18, %v3, %v20
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#CHECK: vfeeb %v0, %v0, %v0, 12
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0xe7 0x00 0x00 0xc0 0x00 0x80
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#CHECK: vfeeb %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x0a 0x80
|
||||
|
||||
#CHECK: vfeebs %v7, %v24, %v9
|
||||
@ -998,13 +1001,16 @@
|
||||
#CHECK: vfeezbs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x04 0x80
|
||||
|
||||
#CHECK: vfeeb %v31, %v31, %v31
|
||||
#CHECK: vfeeb %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x0e 0x80
|
||||
|
||||
#CHECK: vfeef %v0, %v0, %v0
|
||||
#CHECK: vfeef %v0, %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x20 0x80
|
||||
|
||||
#CHECK: vfeef %v18, %v3, %v20
|
||||
#CHECK: vfeef %v0, %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x20 0x80
|
||||
|
||||
#CHECK: vfeef %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x2a 0x80
|
||||
|
||||
#CHECK: vfeefs %v7, %v24, %v9
|
||||
@ -1016,13 +1022,16 @@
|
||||
#CHECK: vfeezfs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x24 0x80
|
||||
|
||||
#CHECK: vfeef %v31, %v31, %v31
|
||||
#CHECK: vfeef %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x2e 0x80
|
||||
|
||||
#CHECK: vfeeh %v0, %v0, %v0
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x10 0x80
|
||||
|
||||
#CHECK: vfeeh %v18, %v3, %v20
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x10 0x80
|
||||
|
||||
#CHECK: vfeeh %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x1a 0x80
|
||||
|
||||
#CHECK: vfeehs %v7, %v24, %v9
|
||||
@ -1034,13 +1043,16 @@
|
||||
#CHECK: vfeezhs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x14 0x80
|
||||
|
||||
#CHECK: vfeeh %v31, %v31, %v31
|
||||
#CHECK: vfeeh %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x1e 0x80
|
||||
|
||||
#CHECK: vfeneb %v0, %v0, %v0
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x81
|
||||
|
||||
#CHECK: vfeneb %v18, %v3, %v20
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x00 0x81
|
||||
|
||||
#CHECK: vfeneb %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x0a 0x81
|
||||
|
||||
#CHECK: vfenebs %v7, %v24, %v9
|
||||
@ -1052,13 +1064,16 @@
|
||||
#CHECK: vfenezbs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x04 0x81
|
||||
|
||||
#CHECK: vfeneb %v31, %v31, %v31
|
||||
#CHECK: vfeneb %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x0e 0x81
|
||||
|
||||
#CHECK: vfenef %v0, %v0, %v0
|
||||
#CHECK: vfenef %v0, %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x20 0x81
|
||||
|
||||
#CHECK: vfenef %v18, %v3, %v20
|
||||
#CHECK: vfenef %v0, %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x20 0x81
|
||||
|
||||
#CHECK: vfenef %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x2a 0x81
|
||||
|
||||
#CHECK: vfenefs %v7, %v24, %v9
|
||||
@ -1070,13 +1085,16 @@
|
||||
#CHECK: vfenezfs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x24 0x81
|
||||
|
||||
#CHECK: vfenef %v31, %v31, %v31
|
||||
#CHECK: vfenef %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x2e 0x81
|
||||
|
||||
#CHECK: vfeneh %v0, %v0, %v0
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x10 0x81
|
||||
|
||||
#CHECK: vfeneh %v18, %v3, %v20
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x10 0x81
|
||||
|
||||
#CHECK: vfeneh %v18, %v3, %v20, 0
|
||||
0xe7 0x23 0x40 0x00 0x1a 0x81
|
||||
|
||||
#CHECK: vfenehs %v7, %v24, %v9
|
||||
@ -1088,7 +1106,7 @@
|
||||
#CHECK: vfenezhs %v7, %v24, %v9
|
||||
0xe7 0x78 0x90 0x30 0x14 0x81
|
||||
|
||||
#CHECK: vfeneh %v31, %v31, %v31
|
||||
#CHECK: vfeneh %v31, %v31, %v31, 0
|
||||
0xe7 0xff 0xf0 0x00 0x1e 0x81
|
||||
|
||||
#CHECK: vfidb %v0, %v0, 0, 0
|
||||
@ -1100,40 +1118,49 @@
|
||||
#CHECK: vfidb %v31, %v31, 7, 15
|
||||
0xe7 0xff 0x00 0xf7 0x3c 0xc7
|
||||
|
||||
#CHECK: vistrb %v0, %v0
|
||||
#CHECK: vistrb %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x5c
|
||||
|
||||
#CHECK: vistrb %v18, %v3
|
||||
#CHECK: vistrb %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x00 0x5c
|
||||
|
||||
#CHECK: vistrb %v18, %v3, 0
|
||||
0xe7 0x23 0x00 0x00 0x08 0x5c
|
||||
|
||||
#CHECK: vistrbs %v7, %v24
|
||||
0xe7 0x78 0x00 0x10 0x04 0x5c
|
||||
|
||||
#CHECK: vistrb %v31, %v31
|
||||
#CHECK: vistrb %v31, %v31, 0
|
||||
0xe7 0xff 0x00 0x00 0x0c 0x5c
|
||||
|
||||
#CHECK: vistrf %v0, %v0
|
||||
#CHECK: vistrf %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x20 0x5c
|
||||
|
||||
#CHECK: vistrf %v18, %v3
|
||||
#CHECK: vistrf %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x20 0x5c
|
||||
|
||||
#CHECK: vistrf %v18, %v3, 0
|
||||
0xe7 0x23 0x00 0x00 0x28 0x5c
|
||||
|
||||
#CHECK: vistrfs %v7, %v24
|
||||
0xe7 0x78 0x00 0x10 0x24 0x5c
|
||||
|
||||
#CHECK: vistrf %v31, %v31
|
||||
#CHECK: vistrf %v31, %v31, 0
|
||||
0xe7 0xff 0x00 0x00 0x2c 0x5c
|
||||
|
||||
#CHECK: vistrh %v0, %v0
|
||||
#CHECK: vistrh %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x10 0x5c
|
||||
|
||||
#CHECK: vistrh %v18, %v3
|
||||
#CHECK: vistrh %v0, %v0, 12
|
||||
0xe7 0x00 0x00 0xc0 0x10 0x5c
|
||||
|
||||
#CHECK: vistrh %v18, %v3, 0
|
||||
0xe7 0x23 0x00 0x00 0x18 0x5c
|
||||
|
||||
#CHECK: vistrhs %v7, %v24
|
||||
0xe7 0x78 0x00 0x10 0x14 0x5c
|
||||
|
||||
#CHECK: vistrh %v31, %v31
|
||||
#CHECK: vistrh %v31, %v31, 0
|
||||
0xe7 0xff 0x00 0x00 0x1c 0x5c
|
||||
|
||||
#CHECK: vfmadb %v0, %v0, %v0, %v0
|
||||
|
||||
@ -319,6 +319,120 @@
|
||||
vfaezfs %v0, %v0
|
||||
vfaezfs %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeb %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeb %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeeb %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeb %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfeeb %v0, %v0, %v0, -1
|
||||
vfeeb %v0, %v0, %v0, 16
|
||||
vfeeb %v0, %v0
|
||||
vfeeb %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeef %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeef %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeef %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeef %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfeef %v0, %v0, %v0, -1
|
||||
vfeef %v0, %v0, %v0, 16
|
||||
vfeef %v0, %v0
|
||||
vfeef %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeh %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeeh %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfeeh %v0, %v0, %v0, -1
|
||||
vfeeh %v0, %v0, %v0, 16
|
||||
vfeeh %v0, %v0
|
||||
vfeeh %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeebs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeebs %v0, %v0, %v0, 0
|
||||
|
||||
vfeebs %v0, %v0
|
||||
vfeebs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeefs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeefs %v0, %v0, %v0, 0
|
||||
|
||||
vfeefs %v0, %v0
|
||||
vfeefs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeehs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeehs %v0, %v0, %v0, 0
|
||||
|
||||
vfeehs %v0, %v0
|
||||
vfeehs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezb %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezb %v0, %v0, %v0, 0
|
||||
|
||||
vfeezb %v0, %v0
|
||||
vfeezb %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezf %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezf %v0, %v0, %v0, 0
|
||||
|
||||
vfeezf %v0, %v0
|
||||
vfeezf %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezh %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezh %v0, %v0, %v0, 0
|
||||
|
||||
vfeezh %v0, %v0
|
||||
vfeezh %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezbs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezbs %v0, %v0, %v0, 0
|
||||
|
||||
vfeezbs %v0, %v0
|
||||
vfeezbs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezfs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezfs %v0, %v0, %v0, 0
|
||||
|
||||
vfeezfs %v0, %v0
|
||||
vfeezfs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeezhs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeezhs %v0, %v0, %v0, 0
|
||||
|
||||
vfeezhs %v0, %v0
|
||||
vfeezhs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfidb %v0, %v0, 0, -1
|
||||
#CHECK: error: invalid operand
|
||||
@ -445,6 +559,72 @@
|
||||
vgmh %v0, -1, 0
|
||||
vgmh %v0, 256, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrb %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrb %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrb %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrb %v0, %v0, 0, 0
|
||||
|
||||
vistrb %v0, %v0, -1
|
||||
vistrb %v0, %v0, 16
|
||||
vistrb %v0
|
||||
vistrb %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrf %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrf %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrf %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrf %v0, %v0, 0, 0
|
||||
|
||||
vistrf %v0, %v0, -1
|
||||
vistrf %v0, %v0, 16
|
||||
vistrf %v0
|
||||
vistrf %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrh %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrh %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrh %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrh %v0, %v0, 0, 0
|
||||
|
||||
vistrh %v0, %v0, -1
|
||||
vistrh %v0, %v0, 16
|
||||
vistrh %v0
|
||||
vistrh %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrbs %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrbs %v0, %v0, 0
|
||||
|
||||
vistrbs %v0
|
||||
vistrbs %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrfs %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrfs %v0, %v0, 0
|
||||
|
||||
vistrfs %v0
|
||||
vistrfs %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vistrhs %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vistrhs %v0, %v0, 0
|
||||
|
||||
vistrhs %v0
|
||||
vistrhs %v0, %v0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vl %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
@ -806,6 +986,112 @@
|
||||
vlvgh %v0, %r0, 4096
|
||||
vlvgh %v0, %r0, 0(%r0)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneb %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeneb %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfeneb %v0, %v0, %v0, -1
|
||||
vfeneb %v0, %v0, %v0, 16
|
||||
vfeneb %v0, %v0
|
||||
vfeneb %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenef %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenef %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenef %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenef %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfenef %v0, %v0, %v0, -1
|
||||
vfenef %v0, %v0, %v0, 16
|
||||
vfenef %v0, %v0
|
||||
vfenef %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneh %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 16
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfeneh %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 0, 0
|
||||
|
||||
vfeneh %v0, %v0, %v0, -1
|
||||
vfeneh %v0, %v0, %v0, 16
|
||||
vfeneh %v0, %v0
|
||||
vfeneh %v0, %v0, %v0, 0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenebs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenebs %v0, %v0, %v0, 0
|
||||
|
||||
vfenebs %v0, %v0
|
||||
vfenebs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenefs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenefs %v0, %v0, %v0, 0
|
||||
|
||||
vfenefs %v0, %v0
|
||||
vfenefs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenehs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenehs %v0, %v0, %v0, 0
|
||||
|
||||
vfenehs %v0, %v0
|
||||
vfenehs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenezb %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenezb %v0, %v0, %v0, 0
|
||||
|
||||
vfenezb %v0, %v0
|
||||
vfenezb %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenezf %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenezf %v0, %v0, %v0, 0
|
||||
|
||||
vfenezf %v0, %v0
|
||||
vfenezf %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenezh %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenezh %v0, %v0, %v0, 0
|
||||
|
||||
vfenezh %v0, %v0
|
||||
vfenezh %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenezbs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenezbs %v0, %v0, %v0, 0
|
||||
|
||||
vfenezbs %v0, %v0
|
||||
vfenezbs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: too few operands
|
||||
#CHECK: vfenezfs %v0, %v0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vfenezfs %v0, %v0, %v0, 0
|
||||
|
||||
vfenezfs %v0, %v0
|
||||
vfenezfs %v0, %v0, %v0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vpdi %v0, %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
|
||||
@ -1394,19 +1394,23 @@
|
||||
vfddb %v31, %v0, %v0
|
||||
vfddb %v18, %v3, %v20
|
||||
|
||||
#CHECK: vfeeb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x80]
|
||||
#CHECK: vfeeb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x80]
|
||||
#CHECK: vfeeb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x80]
|
||||
#CHECK: vfeeb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x80]
|
||||
#CHECK: vfeeb %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x80]
|
||||
#CHECK: vfeeb %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x80]
|
||||
#CHECK: vfeeb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x80]
|
||||
#CHECK: vfeeb %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x80]
|
||||
#CHECK: vfeebs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0x80]
|
||||
#CHECK: vfeezb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x80]
|
||||
#CHECK: vfeezbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x04,0x80]
|
||||
|
||||
vfeeb %v0, %v0, %v0
|
||||
vfeeb %v0, %v0, %v0, 0
|
||||
vfeeb %v0, %v0, %v0, 12
|
||||
vfeeb %v0, %v0, %v15
|
||||
vfeeb %v0, %v0, %v31
|
||||
vfeeb %v0, %v15, %v0
|
||||
@ -1418,19 +1422,23 @@
|
||||
vfeezb %v18, %v3, %v20
|
||||
vfeezbs %v5, %v22, %v7
|
||||
|
||||
#CFECK: vfeef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x80]
|
||||
#CFECK: vfeef %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x80]
|
||||
#CFECK: vfeef %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x80]
|
||||
#CFECK: vfeef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x80]
|
||||
#CFECK: vfeef %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x80]
|
||||
#CFECK: vfeef %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x80]
|
||||
#CFECK: vfeef %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x80]
|
||||
#CFECK: vfeef %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x80]
|
||||
#CFECK: vfeefs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x80]
|
||||
#CFECK: vfeezf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x80]
|
||||
#CFECK: vfeezfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x24,0x80]
|
||||
|
||||
vfeef %v0, %v0, %v0
|
||||
vfeef %v0, %v0, %v0, 0
|
||||
vfeef %v0, %v0, %v0, 12
|
||||
vfeef %v0, %v0, %v15
|
||||
vfeef %v0, %v0, %v31
|
||||
vfeef %v0, %v15, %v0
|
||||
@ -1442,19 +1450,23 @@
|
||||
vfeezf %v18, %v3, %v20
|
||||
vfeezfs %v5, %v22, %v7
|
||||
|
||||
#CHECK: vfeeh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x80]
|
||||
#CHECK: vfeeh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x80]
|
||||
#CHECK: vfeeh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x80]
|
||||
#CHECK: vfeeh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x80]
|
||||
#CHECK: vfeeh %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x80]
|
||||
#CHECK: vfeeh %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x80]
|
||||
#CHECK: vfeeh %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x80]
|
||||
#CHECK: vfeeh %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x80]
|
||||
#CHECK: vfeehs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x80]
|
||||
#CHECK: vfeezh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x80]
|
||||
#CHECK: vfeezhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x14,0x80]
|
||||
|
||||
vfeeh %v0, %v0, %v0
|
||||
vfeeh %v0, %v0, %v0, 0
|
||||
vfeeh %v0, %v0, %v0, 12
|
||||
vfeeh %v0, %v0, %v15
|
||||
vfeeh %v0, %v0, %v31
|
||||
vfeeh %v0, %v15, %v0
|
||||
@ -1466,19 +1478,23 @@
|
||||
vfeezh %v18, %v3, %v20
|
||||
vfeezhs %v5, %v22, %v7
|
||||
|
||||
#CHECK: vfeneb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x81]
|
||||
#CHECK: vfeneb %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x81]
|
||||
#CHECK: vfeneb %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x81]
|
||||
#CHECK: vfeneb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x81]
|
||||
#CHECK: vfeneb %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x81]
|
||||
#CHECK: vfeneb %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x81]
|
||||
#CHECK: vfeneb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x81]
|
||||
#CHECK: vfeneb %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x81]
|
||||
#CHECK: vfenebs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x04,0x81]
|
||||
#CHECK: vfenezb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x0a,0x81]
|
||||
#CHECK: vfenezbs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x04,0x81]
|
||||
|
||||
vfeneb %v0, %v0, %v0
|
||||
vfeneb %v0, %v0, %v0, 0
|
||||
vfeneb %v0, %v0, %v0, 12
|
||||
vfeneb %v0, %v0, %v15
|
||||
vfeneb %v0, %v0, %v31
|
||||
vfeneb %v0, %v15, %v0
|
||||
@ -1490,19 +1506,23 @@
|
||||
vfenezb %v18, %v3, %v20
|
||||
vfenezbs %v5, %v22, %v7
|
||||
|
||||
#CFECK: vfenef %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x81]
|
||||
#CFECK: vfenef %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x81]
|
||||
#CFECK: vfenef %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x81]
|
||||
#CFECK: vfenef %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x22,0x81]
|
||||
#CFECK: vfenef %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x81]
|
||||
#CFECK: vfenef %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x81]
|
||||
#CFECK: vfenef %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x81]
|
||||
#CFECK: vfenef %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x2a,0x81]
|
||||
#CFECK: vfenefs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x24,0x81]
|
||||
#CFECK: vfenezf %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x2a,0x81]
|
||||
#CFECK: vfenezfs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x24,0x81]
|
||||
|
||||
vfenef %v0, %v0, %v0
|
||||
vfenef %v0, %v0, %v0, 0
|
||||
vfenef %v0, %v0, %v0, 12
|
||||
vfenef %v0, %v0, %v15
|
||||
vfenef %v0, %v0, %v31
|
||||
vfenef %v0, %v15, %v0
|
||||
@ -1514,19 +1534,23 @@
|
||||
vfenezf %v18, %v3, %v20
|
||||
vfenezfs %v5, %v22, %v7
|
||||
|
||||
#CHECK: vfeneh %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x81]
|
||||
#CHECK: vfeneh %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x81]
|
||||
#CHECK: vfeneh %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x81]
|
||||
#CHECK: vfeneh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x12,0x81]
|
||||
#CHECK: vfeneh %v0, %v15, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x81]
|
||||
#CHECK: vfeneh %v15, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x81]
|
||||
#CHECK: vfeneh %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x81]
|
||||
#CHECK: vfeneh %v18, %v3, %v20, 0 # encoding: [0xe7,0x23,0x40,0x00,0x1a,0x81]
|
||||
#CHECK: vfenehs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x10,0x14,0x81]
|
||||
#CHECK: vfenezh %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x20,0x1a,0x81]
|
||||
#CHECK: vfenezhs %v5, %v22, %v7 # encoding: [0xe7,0x56,0x70,0x30,0x14,0x81]
|
||||
|
||||
vfeneh %v0, %v0, %v0
|
||||
vfeneh %v0, %v0, %v0, 0
|
||||
vfeneh %v0, %v0, %v0, 12
|
||||
vfeneh %v0, %v0, %v15
|
||||
vfeneh %v0, %v0, %v31
|
||||
vfeneh %v0, %v15, %v0
|
||||
@ -1554,15 +1578,19 @@
|
||||
vfidb %v31, %v0, 0, 0
|
||||
vfidb %v14, %v17, 4, 10
|
||||
|
||||
#CHECK: vistrb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5c]
|
||||
#CHECK: vistrb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5c]
|
||||
#CHECK: vistrb %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x08,0x5c]
|
||||
#CHECK: vistrb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x5c]
|
||||
#CHECK: vistrb %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x5c]
|
||||
#CHECK: vistrb %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x5c]
|
||||
#CHECK: vistrb %v18, %v3, 0 # encoding: [0xe7,0x23,0x00,0x00,0x08,0x5c]
|
||||
#CHECK: vistrbs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x04,0x5c]
|
||||
|
||||
vistrb %v0, %v0
|
||||
vistrb %v0, %v0, 0
|
||||
vistrb %v0, %v0, 12
|
||||
vistrb %v0, %v15
|
||||
vistrb %v0, %v31
|
||||
vistrb %v15, %v0
|
||||
@ -1570,15 +1598,19 @@
|
||||
vistrb %v18, %v3
|
||||
vistrbs %v5, %v22
|
||||
|
||||
#CBECK: vistrf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5c]
|
||||
#CBECK: vistrf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5c]
|
||||
#CBECK: vistrf %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x28,0x5c]
|
||||
#CBECK: vistrf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x5c]
|
||||
#CBECK: vistrf %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x5c]
|
||||
#CBECK: vistrf %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x5c]
|
||||
#CBECK: vistrf %v18, %v3, 0 # encoding: [0xe7,0x23,0x00,0x00,0x28,0x5c]
|
||||
#CBECK: vistrfs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x24,0x5c]
|
||||
|
||||
vistrf %v0, %v0
|
||||
vistrf %v0, %v0, 0
|
||||
vistrf %v0, %v0, 12
|
||||
vistrf %v0, %v15
|
||||
vistrf %v0, %v31
|
||||
vistrf %v15, %v0
|
||||
@ -1586,15 +1618,19 @@
|
||||
vistrf %v18, %v3
|
||||
vistrfs %v5, %v22
|
||||
|
||||
#CHECK: vistrh %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5c]
|
||||
#CHECK: vistrh %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5c]
|
||||
#CHECK: vistrh %v18, %v3 # encoding: [0xe7,0x23,0x00,0x00,0x18,0x5c]
|
||||
#CHECK: vistrh %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v15, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x5c]
|
||||
#CHECK: vistrh %v15, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x5c]
|
||||
#CHECK: vistrh %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x5c]
|
||||
#CHECK: vistrh %v18, %v3, 0 # encoding: [0xe7,0x23,0x00,0x00,0x18,0x5c]
|
||||
#CHECK: vistrhs %v5, %v22 # encoding: [0xe7,0x56,0x00,0x10,0x14,0x5c]
|
||||
|
||||
vistrh %v0, %v0
|
||||
vistrh %v0, %v0, 0
|
||||
vistrh %v0, %v0, 12
|
||||
vistrh %v0, %v15
|
||||
vistrh %v0, %v31
|
||||
vistrh %v15, %v0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user