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implement support for 64-bit add/sub, fix a broken assertion for 64-bit
return. Allow the udiv breaker-upper to work with any non-zero constant operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23066 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -909,7 +909,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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// If this is a divide by constant, we can emit code using some magic
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// constants to implement it as a multiply instead.
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unsigned Imm;
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if (isIntImmediate(N->getOperand(1), Imm) && (signed)Imm > 1) {
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if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
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SDOperand Result = Select(BuildUDIVSequence(N));
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assert(Result.ResNo == 0);
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CurDAG->ReplaceAllUsesWith(N, Result.Val);
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@ -1129,6 +1129,62 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(0)));
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break;
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}
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case ISD::ADD_PARTS: {
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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unsigned Imm;
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bool ME, ZE;
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if (isIntImmediate(N->getOperand(3), Imm)) {
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ME = (signed)Imm == -1;
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ZE = Imm == 0;
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}
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std::vector<SDOperand> Result;
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SDOperand CarryFromLo;
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if (isIntImmediate(N->getOperand(2), Imm) &&
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((signed)Imm >= -32768 || (signed)Imm < 32768)) {
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// Codegen the low 32 bits of the add. Interestingly, there is no
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// shifted form of add immediate carrying.
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CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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LHSL, getI32Imm(Imm));
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} else {
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CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
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LHSL, Select(N->getOperand(2)));
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}
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Result.push_back(CarryFromLo);
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CarryFromLo = CarryFromLo.getValue(1);
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// Codegen the high 32 bits, adding zero, minus one, or the full value
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// along with the carry flag produced by addc/addic.
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SDOperand ResultHi;
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if (ZE)
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ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
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else if (ME)
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ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
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else
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ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
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Select(N->getOperand(3)), CarryFromLo);
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Result.push_back(ResultHi);
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CurDAG->ReplaceAllUsesWith(N, Result);
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return Result[Op.ResNo];
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}
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case ISD::SUB_PARTS: {
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SDOperand LHSL = Select(N->getOperand(0));
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SDOperand LHSH = Select(N->getOperand(1));
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SDOperand RHSL = Select(N->getOperand(2));
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SDOperand RHSH = Select(N->getOperand(3));
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std::vector<SDOperand> Result;
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Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
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RHSL, LHSL));
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Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
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Result[0].getValue(1)));
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CurDAG->ReplaceAllUsesWith(N, Result);
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return Result[Op.ResNo];
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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@ -1419,7 +1475,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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if (N->getNumOperands() > 2) {
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assert(N->getOperand(1).getValueType() == MVT::i32 &&
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N->getOperand(2).getValueType() == MVT::i32 &&
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N->getNumOperands() == 2 && "Unknown two-register ret value!");
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N->getNumOperands() == 3 && "Unknown two-register ret value!");
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Val = Select(N->getOperand(2));
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Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
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}
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