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[X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.

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This also fixes a bug where negative immediates below -128 were not being reported as errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-10-11 18:27:24 +00:00
parent 6bb2edf33a
commit a9d6f4a14a
5 changed files with 15 additions and 27 deletions
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23
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -718,7 +718,6 @@ private:
bool ParseDirectiveWord(unsigned Size, SMLoc L);
bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
bool processInstruction(MCInst &Inst, const OperandVector &Ops);
/// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
@ -2401,22 +2400,6 @@ static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
}
bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
switch (Inst.getOpcode()) {
default: return true;
case X86::INT:
X86Operand &Op = static_cast<X86Operand &>(*Ops[1]);
assert(Op.isImm() && "expected immediate");
int64_t Res;
if (!Op.getImm()->evaluateAsAbsolute(Res) || Res > 255) {
Error(Op.getStartLoc(), "interrupt vector must be in range [0-255]");
return false;
}
return true;
}
llvm_unreachable("handle the instruction appropriately");
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
switch (Inst.getOpcode()) {
default: return false;
@ -2579,9 +2562,6 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
isParsingIntelSyntax())) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
if (!validateInstruction(Inst, Operands))
return true;
// Some instructions need post-processing to, for example, tweak which
// encoding is selected. Loop on it while changes happen so the
// individual transformations can chain off each other.
@ -2825,9 +2805,6 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
unsigned NumSuccessfulMatches =
std::count(std::begin(Match), std::end(Match), Match_Success);
if (NumSuccessfulMatches == 1) {
if (!validateInstruction(Inst, Operands))
return true;
// Some instructions need post-processing to, for example, tweak which
// encoding is selected. Loop on it while changes happen so the individual
// transformations can chain off each other.

2
lib/Target/X86/X86InstrSystem.td
View File

@ -44,7 +44,7 @@ def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
let SchedRW = [WriteSystem] in {
def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
[(int_x86_int imm:$trap)], IIC_INT>;

2
test/CodeGen/X86/int-intrinsic.ll
View File

@ -11,7 +11,7 @@ bb.entry:
ret void
}
; CHECK: int $-128
; CHECK: int $128
; CHECK: ret
define void @primitive_int128 () {
bb.entry:

7
test/MC/X86/validate-inst-att.s
View File

@ -2,6 +2,11 @@
.text
int $65535
# CHECK: error: interrupt vector must be in range [0-255]
# CHECK: error: invalid operand for instruction
# CHECK: int $65535
# CHECK: ^
int $-129
# CHECK: error: invalid operand for instruction
# CHECK: int $-129
# CHECK: ^

8
test/MC/X86/validate-inst-intel.s
View File

@ -3,7 +3,13 @@
.text
int 65535
# CHECK: error: interrupt vector must be in range [0-255]
# CHECK: error: invalid operand for instruction
# CHECK: int 65535
# CHECK: ^
.text
int -129
# CHECK: error: invalid operand for instruction
# CHECK: int -129
# CHECK: ^