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Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
70a0915cd1
commit
aa3402e280
@ -1863,7 +1863,7 @@ defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
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}
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multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
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def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rn_wb, GPR:$Rt),
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def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode3:$addr), IndexModePre,
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LdMiscFrm, itin,
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opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
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@ -1874,7 +1874,7 @@ multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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}
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def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rn_wb, GPR:$Rt),
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def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am3offset:$offset), IndexModePost,
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LdMiscFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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@ -1893,7 +1893,7 @@ defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
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defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
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defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
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let hasExtraDefRegAllocReq = 1 in {
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def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2),
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def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
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(ins addrmode3:$addr), IndexModePre,
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LdMiscFrm, IIC_iLoad_d_ru,
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"ldrd", "\t$Rt, $Rt2, $addr!",
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@ -1904,9 +1904,8 @@ def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2),
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2),
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def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
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(ins GPR:$Rn, am3offset:$offset), IndexModePost,
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LdMiscFrm, IIC_iLoad_d_ru,
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"ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
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@ -1918,7 +1917,6 @@ def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rn_wb, GPR:$Rt, GPR:$Rt2),
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let Inst{19-16} = Rn;
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let Inst{11-8} = offset{7-4}; // imm7_4/zero
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let Inst{3-0} = offset{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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} // hasExtraDefRegAllocReq = 1
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} // mayLoad = 1, neverHasSideEffects = 1
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@ -1955,17 +1953,17 @@ def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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let Inst{11-0} = addr{11-0};
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt),
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def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt),
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def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$base_wb, GPR:$Rt),
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def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
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(ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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@ -1983,10 +1981,7 @@ def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
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StMiscFrm, IIC_iStore_d_r,
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"strd", "\t$Rt, $src2, $addr", []>,
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Requires<[IsARM, HasV5TE]> {
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let Inst{21} = 0;
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}
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"strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
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// Indexed stores
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def STR_PRE_REG : AI2stridx_reg<0, 1, (outs GPR:$Rn_wb),
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@ -2075,38 +2070,14 @@ def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
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(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
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StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$src1, $src2, [$base, $offset]!",
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"$base = $base_wb", []> {
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bits<4> src1;
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bits<4> base;
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bits<10> offset;
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = base;
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let Inst{15-12} = src1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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"$base = $base_wb", []>;
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// For disassembly only
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def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
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(ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
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StMiscFrm, IIC_iStore_d_ru,
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"strd", "\t$src1, $src2, [$base], $offset",
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"$base = $base_wb", []> {
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bits<4> src1;
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bits<4> base;
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bits<10> offset;
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let Inst{23} = offset{8}; // U bit
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let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
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let Inst{19-16} = base;
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let Inst{15-12} = src1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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"$base = $base_wb", []>;
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} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
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// STRT, STRBT, and STRHT are for disassembly only.
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@ -1919,9 +1919,11 @@ cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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bool ARMAsmParser::
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cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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// Create a writeback register dummy placeholder.
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Inst.addOperand(MCOperand::CreateImm(0));
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((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
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((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
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((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
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return true;
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@ -1460,7 +1460,7 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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&& "Invalid arguments");
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// Operand 0 of a pre- and post-indexed store is the address base writeback.
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if (isPrePost) {
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if (isPrePost && isStore) {
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assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
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"Reg operand expected");
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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@ -1485,6 +1485,15 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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++OpIdx;
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}
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// After dst of a pre- and post-indexed load is the address base writeback.
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if (isPrePost && !isStore) {
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assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
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"Reg operand expected");
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRn(insn))));
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++OpIdx;
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}
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// Disassemble the base operand.
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if (OpIdx >= NumOps)
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return false;
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