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[Hexagon] Rerun bit tracker on new instructions in RIE
Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
f39cea0a71
commit
aa3e2e6820
@ -1042,6 +1042,15 @@ bool BT::reached(const MachineBasicBlock *B) const {
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}
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// Visit an individual instruction. This could be a newly added instruction,
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// or one that has been modified by an optimization.
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void BT::visit(const llvm::MachineInstr &MI) {
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assert(!MI.isBranch() && "Only non-branches are allowed");
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InstrExec.insert(&MI);
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visitNonBranch(MI);
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}
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void BT::reset() {
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EdgeExec.clear();
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InstrExec.clear();
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@ -49,6 +49,7 @@ struct BitTracker {
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void put(RegisterRef RR, const RegisterCell &RC);
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void subst(RegisterRef OldRR, RegisterRef NewRR);
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bool reached(const MachineBasicBlock *B) const;
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void visit(const MachineInstr &MI);
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private:
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void visitPHI(const MachineInstr &PI);
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@ -1294,18 +1294,20 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
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const DebugLoc &DL = MI->getDebugLoc();
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const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
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unsigned NewR = MRI.createVirtualRegister(FRC);
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BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
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.addReg(RS.Reg, 0, RS.Sub);
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MachineInstr *CopyI =
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BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
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.addReg(RS.Reg, 0, RS.Sub);
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HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
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// Do not update the bit tracker. This pass can create copies between
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// registers that don't have the exact same values. Updating the
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// tracker here may be tricky. E.g.
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// This pass can create copies between registers that don't have the
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// exact same values. Updating the tracker has to involve updating
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// all dependent cells. Example:
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// vreg1 = inst vreg2 ; vreg1 != vreg2, but used bits are equal
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//
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// vreg3 = copy vreg2 ; <- inserted
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// ... = vreg3 ; <- replaced from vreg2
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// Indirectly, we can create a "copy" between vreg1 and vreg2 even
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// though their exact values do not match.
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BT.visit(*CopyI);
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Changed = true;
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break;
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}
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208
test/CodeGen/Hexagon/bit-rie.ll
Normal file
208
test/CodeGen/Hexagon/bit-rie.ll
Normal file
@ -0,0 +1,208 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: LBB0{{.*}}if.end
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; CHECK: r[[REG:[0-9]+]] = zxth
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; CHECK: lsr(r[[REG]],
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target triple = "hexagon"
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@g0 = external constant [146 x i16], align 8
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@g1 = external constant [0 x i16], align 2
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define void @fred(i32* nocapture readonly %p0, i16 signext %p1, i16* nocapture %p2, i16 signext %p3, i16 signext %p4, i16 signext %p5) #0 {
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entry:
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%conv = sext i16 %p1 to i32
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%0 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %conv, i32 1)
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%1 = tail call i32 @llvm.hexagon.A2.sath(i32 %0)
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%2 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 3, i32 %1)
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%conv3 = sext i16 %p4 to i32
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%cmp144 = icmp sgt i16 %p4, 0
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br i1 %cmp144, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %p0, %entry ]
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%i.0146.apmt = phi i32 [ %inc.apmt, %for.body ], [ 0, %entry ]
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%L_temp1.0145 = phi i32 [ %5, %for.body ], [ 1, %entry ]
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%3 = load i32, i32* %arrayidx.phi, align 4, !tbaa !1
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%4 = tail call i32 @llvm.hexagon.A2.abssat(i32 %3)
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%5 = tail call i32 @llvm.hexagon.A2.max(i32 %L_temp1.0145, i32 %4)
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%inc.apmt = add nuw nsw i32 %i.0146.apmt, 1
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%exitcond151 = icmp eq i32 %inc.apmt, %conv3
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%arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
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br i1 %exitcond151, label %for.end, label %for.body, !llvm.loop !5
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for.end: ; preds = %for.body, %entry
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%L_temp1.0.lcssa = phi i32 [ 1, %entry ], [ %5, %for.body ]
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%6 = tail call i32 @llvm.hexagon.S2.clbnorm(i32 %L_temp1.0.lcssa)
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%arrayidx6 = getelementptr inbounds [146 x i16], [146 x i16]* @g0, i32 0, i32 %conv3
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%7 = load i16, i16* %arrayidx6, align 2, !tbaa !7
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%conv7 = sext i16 %7 to i32
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%8 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %6, i32 %conv7)
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br i1 %cmp144, label %for.body14.lr.ph, label %for.end29
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for.body14.lr.ph: ; preds = %for.end
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%sext132 = shl i32 %8, 16
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%conv17 = ashr exact i32 %sext132, 16
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br label %for.body14
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for.body14: ; preds = %for.body14, %for.body14.lr.ph
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%arrayidx16.phi = phi i32* [ %p0, %for.body14.lr.ph ], [ %arrayidx16.inc, %for.body14 ]
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%i.1143.apmt = phi i32 [ 0, %for.body14.lr.ph ], [ %inc28.apmt, %for.body14 ]
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%L_temp.0142 = phi i32 [ 0, %for.body14.lr.ph ], [ %12, %for.body14 ]
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%9 = load i32, i32* %arrayidx16.phi, align 4, !tbaa !1
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%10 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %9, i32 %conv17)
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%11 = tail call i32 @llvm.hexagon.A2.asrh(i32 %10)
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%sext133 = shl i32 %11, 16
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%conv23 = ashr exact i32 %sext133, 16
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%12 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %L_temp.0142, i32 %conv23, i32 %conv23)
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%inc28.apmt = add nuw nsw i32 %i.1143.apmt, 1
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%exitcond = icmp eq i32 %inc28.apmt, %conv3
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%arrayidx16.inc = getelementptr i32, i32* %arrayidx16.phi, i32 1
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br i1 %exitcond, label %for.end29, label %for.body14
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for.end29: ; preds = %for.body14, %for.end
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%L_temp.0.lcssa = phi i32 [ 0, %for.end ], [ %12, %for.body14 ]
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%13 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %conv3, i32 1)
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%cmp31 = icmp sgt i32 %13, 0
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br i1 %cmp31, label %if.then, label %if.end
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if.then: ; preds = %for.end29
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%arrayidx34 = getelementptr inbounds [0 x i16], [0 x i16]* @g1, i32 0, i32 %conv3
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%14 = load i16, i16* %arrayidx34, align 2, !tbaa !7
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%cmp.i = icmp eq i32 %L_temp.0.lcssa, -2147483648
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%cmp1.i = icmp eq i16 %14, -32768
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%or.cond.i = and i1 %cmp.i, %cmp1.i
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br i1 %or.cond.i, label %if.end, label %if.else.i
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if.else.i: ; preds = %if.then
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%conv3.i = sext i16 %14 to i32
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%15 = tail call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %L_temp.0.lcssa, i32 %conv3.i) #2
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%16 = tail call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %conv3.i, i32 %L_temp.0.lcssa) #2
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%conv5.i = trunc i64 %16 to i32
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%phitmp = and i32 %conv5.i, 65535
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br label %if.end
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if.end: ; preds = %if.else.i, %if.then, %for.end29
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%L_temp.2 = phi i32 [ %L_temp.0.lcssa, %for.end29 ], [ %15, %if.else.i ], [ 2147483647, %if.then ]
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%lsb.0 = phi i32 [ 0, %for.end29 ], [ %phitmp, %if.else.i ], [ 65535, %if.then ]
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%sext = shl i32 %8, 16
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%conv35 = ashr exact i32 %sext, 16
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%17 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %conv35, i32 16)
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%18 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %17, i32 1)
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%19 = tail call i32 @llvm.hexagon.A2.sath(i32 %18)
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%20 = tail call i32 @llvm.hexagon.S2.clbnorm(i32 %L_temp.2)
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%sext123 = shl i32 %20, 16
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%conv38 = ashr exact i32 %sext123, 16
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%sext124 = shl i32 %19, 16
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%conv39 = ashr exact i32 %sext124, 16
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%21 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv38, i32 %conv39)
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%22 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %L_temp.2, i32 %conv38)
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%23 = tail call i32 @llvm.hexagon.A2.zxth(i32 %lsb.0)
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%24 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 16, i32 %conv38)
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%25 = tail call i32 @llvm.hexagon.S2.lsr.r.r(i32 %23, i32 %24)
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%sext125 = shl i32 %25, 16
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%conv45 = ashr exact i32 %sext125, 16
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%26 = tail call i32 @llvm.hexagon.A2.addsat(i32 %22, i32 %conv45)
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%sext126 = shl i32 %2, 16
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%conv46 = ashr exact i32 %sext126, 16
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%sext127 = shl i32 %21, 16
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%conv47 = ashr exact i32 %sext127, 16
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%27 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv46, i32 %conv47)
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%sext128 = shl i32 %27, 16
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%conv49 = ashr exact i32 %sext128, 16
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%cmp50 = icmp sgt i32 %sext128, 327679
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%tobool = icmp eq i16 %p5, 0
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%or.cond = or i1 %tobool, %cmp50
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br i1 %or.cond, label %if.else68, label %if.then53
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if.then53: ; preds = %if.end
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%28 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %conv49, i32 1)
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%29 = tail call i32 @llvm.hexagon.A2.sath(i32 %28)
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%30 = tail call i32 @llvm.hexagon.A2.subsat(i32 %26, i32 1276901417)
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%cmp56 = icmp slt i32 %30, 0
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br i1 %cmp56, label %if.then58, label %if.else
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if.then58: ; preds = %if.then53
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%sext131 = shl i32 %29, 16
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%conv59 = ashr exact i32 %sext131, 16
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%31 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv59, i32 2)
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br label %if.end80
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if.else: ; preds = %if.then53
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%32 = tail call i32 @llvm.hexagon.A2.subsat(i32 %26, i32 1805811301)
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%cmp61 = icmp slt i32 %32, 0
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br i1 %cmp61, label %if.then63, label %if.end80
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if.then63: ; preds = %if.else
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%sext130 = shl i32 %29, 16
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%conv64 = ashr exact i32 %sext130, 16
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%33 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv64, i32 1)
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br label %if.end80
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if.else68: ; preds = %if.end
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%34 = tail call i32 @llvm.hexagon.A2.subsat(i32 %26, i32 1518500250)
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%cmp69 = icmp slt i32 %34, 0
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br i1 %cmp69, label %if.then71, label %if.end74
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if.then71: ; preds = %if.else68
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%35 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv49, i32 1)
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br label %if.end74
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if.end74: ; preds = %if.then71, %if.else68
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%m.0.in = phi i32 [ %35, %if.then71 ], [ %27, %if.else68 ]
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br i1 %tobool, label %if.end80, label %if.then76
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if.then76: ; preds = %if.end74
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%sext129 = shl i32 %m.0.in, 16
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%conv77 = ashr exact i32 %sext129, 16
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%36 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %conv77, i32 5)
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br label %if.end80
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if.end80: ; preds = %if.end74, %if.then76, %if.then58, %if.then63, %if.else
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%m.1.in = phi i32 [ %31, %if.then58 ], [ %33, %if.then63 ], [ %29, %if.else ], [ %36, %if.then76 ], [ %m.0.in, %if.end74 ]
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%m.1 = trunc i32 %m.1.in to i16
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%cmp.i135 = icmp slt i16 %m.1, 0
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%var_out.0.i136 = select i1 %cmp.i135, i16 0, i16 %m.1
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%conv81 = sext i16 %p3 to i32
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%37 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %conv81, i32 1)
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%conv82 = trunc i32 %37 to i16
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%cmp.i134 = icmp sgt i16 %var_out.0.i136, %conv82
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%var_out.0.i = select i1 %cmp.i134, i16 %conv82, i16 %var_out.0.i136
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store i16 %var_out.0.i, i16* %p2, align 2, !tbaa !7
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ret void
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}
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declare i32 @llvm.hexagon.A2.abssat(i32) #2
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declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) #2
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declare i32 @llvm.hexagon.A2.addsat(i32, i32) #2
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declare i32 @llvm.hexagon.A2.asrh(i32) #2
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declare i32 @llvm.hexagon.A2.max(i32, i32) #2
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declare i32 @llvm.hexagon.A2.sath(i32) #2
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declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #2
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declare i32 @llvm.hexagon.A2.subsat(i32, i32) #2
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declare i32 @llvm.hexagon.A2.zxth(i32) #2
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declare i32 @llvm.hexagon.M2.hmmpyl.s1(i32, i32) #2
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declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) #2
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declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #2
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declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2
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declare i32 @llvm.hexagon.S2.clbnorm(i32) #2
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declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) #2
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declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #2
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declare void @llvm.lifetime.end(i64, i8* nocapture) #1
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declare void @llvm.lifetime.start(i64, i8* nocapture) #1
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { argmemonly nounwind }
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attributes #2 = { nounwind readnone }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = distinct !{!5, !6}
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!6 = !{!"llvm.loop.threadify", i32 81508608}
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!7 = !{!8, !8, i64 0}
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!8 = !{!"short", !3, i64 0}
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!9 = distinct !{!9, !10}
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!10 = !{!"llvm.loop.threadify", i32 1441813}
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!11 = distinct !{!11, !10}
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