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[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284191 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Konstantin Zhuravlyov
parent
15a3555c6d
commit
aa6ce79914
@ -2682,15 +2682,19 @@ Following notations are used for specifying relocation calculations:
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AMDGPU Backend generates *Elf64_Rela* relocation records with the following
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supported relocation types:
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===================== ===== ========== ====================
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Relocation type Value Field Calculation
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===================== ===== ========== ====================
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``R_AMDGPU_NONE`` 0 ``none`` ``none``
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``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF
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``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32
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``R_AMDGPU_ABS64`` 3 ``word64`` S + A
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``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
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``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
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``R_AMDGPU_ABS32`` 6 ``word32`` S + A
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``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
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===================== ===== ========== ====================
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========================== ===== ========== ==============================
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Relocation type Value Field Calculation
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========================== ===== ========== ==============================
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``R_AMDGPU_NONE`` 0 ``none`` ``none``
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``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF
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``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32
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``R_AMDGPU_ABS64`` 3 ``word64`` S + A
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``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
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``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
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``R_AMDGPU_ABS32`` 6 ``word32`` S + A
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``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
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``R_AMDGPU_GOTPCREL32_LO`` 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF
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``R_AMDGPU_GOTPCREL32_HI`` 9 ``word32`` (G + GOT + A - P) >> 32
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``R_AMDGPU_REL32_LO`` 10 ``word32`` (S + A - P) & 0xFFFFFFFF
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``R_AMDGPU_REL32_HI`` 11 ``word32`` (S + A - P) >> 32
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========================== ===== ========== ==============================
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@ -2,11 +2,15 @@
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#error "ELF_RELOC must be defined"
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#endif
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ELF_RELOC(R_AMDGPU_NONE, 0)
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ELF_RELOC(R_AMDGPU_ABS32_LO, 1)
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ELF_RELOC(R_AMDGPU_ABS32_HI, 2)
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ELF_RELOC(R_AMDGPU_ABS64, 3)
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ELF_RELOC(R_AMDGPU_REL32, 4)
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ELF_RELOC(R_AMDGPU_REL64, 5)
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ELF_RELOC(R_AMDGPU_ABS32, 6)
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ELF_RELOC(R_AMDGPU_GOTPCREL, 7)
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ELF_RELOC(R_AMDGPU_NONE, 0)
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ELF_RELOC(R_AMDGPU_ABS32_LO, 1)
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ELF_RELOC(R_AMDGPU_ABS32_HI, 2)
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ELF_RELOC(R_AMDGPU_ABS64, 3)
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ELF_RELOC(R_AMDGPU_REL32, 4)
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ELF_RELOC(R_AMDGPU_REL64, 5)
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ELF_RELOC(R_AMDGPU_ABS32, 6)
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ELF_RELOC(R_AMDGPU_GOTPCREL, 7)
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ELF_RELOC(R_AMDGPU_GOTPCREL32_LO, 8)
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ELF_RELOC(R_AMDGPU_GOTPCREL32_HI, 9)
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ELF_RELOC(R_AMDGPU_REL32_LO, 10)
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ELF_RELOC(R_AMDGPU_REL32_HI, 11)
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@ -3,13 +3,18 @@
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# CHECK: Relocations [
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# CHECK: Section (2) .rela.text {
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# CHECK: 0x0 R_AMDGPU_NONE main 0x0
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# CHECK: 0x8 R_AMDGPU_ABS32_LO - 0x0
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# CHECK: 0x10 R_AMDGPU_ABS32_HI - 0x0
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# CHECK: 0x18 R_AMDGPU_ABS64 - 0x0
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# CHECK: 0x20 R_AMDGPU_REL32 - 0x0
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# CHECK: 0x28 R_AMDGPU_REL64 - 0x0
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# CHECK: 0x30 R_AMDGPU_ABS32 - 0x0
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# CHECK: 0x0 R_AMDGPU_NONE - 0x0
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# CHECK: 0x2 R_AMDGPU_ABS32_LO - 0x0
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# CHECK: 0x4 R_AMDGPU_ABS32_HI - 0x0
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# CHECK: 0x6 R_AMDGPU_ABS64 - 0x0
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# CHECK: 0x8 R_AMDGPU_REL32 - 0x0
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# CHECK: 0x10 R_AMDGPU_REL64 - 0x0
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# CHECK: 0x12 R_AMDGPU_ABS32 - 0x0
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# CHECK: 0x14 R_AMDGPU_GOTPCREL - 0x0
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# CHECK: 0x16 R_AMDGPU_GOTPCREL32_LO - 0x0
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# CHECK: 0x18 R_AMDGPU_GOTPCREL32_HI - 0x0
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# CHECK: 0x20 R_AMDGPU_REL32_LO - 0x0
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# CHECK: 0x22 R_AMDGPU_REL32_HI - 0x0
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# CHECK: }
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# CHECK: ]
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@ -32,26 +37,41 @@ Sections:
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AddressAlign: 0x08
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Relocations:
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- Offset: 0x0
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Symbol: main
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Symbol: s0
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Type: R_AMDGPU_NONE
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- Offset: 0x8
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Symbol: a
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- Offset: 0x2
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Symbol: s1
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Type: R_AMDGPU_ABS32_LO
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- Offset: 0x10
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Symbol: b
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- Offset: 0x4
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Symbol: s2
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Type: R_AMDGPU_ABS32_HI
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- Offset: 0x18
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Symbol: c
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- Offset: 0x6
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Symbol: s3
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Type: R_AMDGPU_ABS64
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- Offset: 0x20
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Symbol: d
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- Offset: 0x8
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Symbol: s4
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Type: R_AMDGPU_REL32
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- Offset: 0x28
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Symbol: e
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- Offset: 0x10
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Symbol: s5
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Type: R_AMDGPU_REL64
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- Offset: 0x30
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Symbol: f
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- Offset: 0x12
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Symbol: s6
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Type: R_AMDGPU_ABS32
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- Offset: 0x14
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Symbol: s7
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Type: R_AMDGPU_GOTPCREL
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- Offset: 0x16
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Symbol: s8
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Type: R_AMDGPU_GOTPCREL32_LO
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- Offset: 0x18
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Symbol: s9
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Type: R_AMDGPU_GOTPCREL32_HI
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- Offset: 0x20
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Symbol: s10
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Type: R_AMDGPU_REL32_LO
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- Offset: 0x22
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Symbol: s11
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Type: R_AMDGPU_REL32_HI
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Symbols:
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Local:
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