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[DAGCombiner] Fix infinite loop in vector mul/shl combining
We have the following DAGCombiner transformations: (mul (shl X, c1), c2) -> (mul X, c2 << c1) (mul (shl X, C), Y) -> (shl (mul X, Y), C) (shl (mul x, c1), c2) -> (mul x, c1 << c2) Usually the constant shift is optimised by SelectionDAG::getNode when it is constructed, by SelectionDAG::FoldConstantArithmetic, but when we're dealing with vectors and one of those vector constants contains an undef element FoldConstantArithmetic does not fold and we enter an infinite loop. Fix this by making FoldConstantArithmetic use getNode to decide how to fold each vector element, the same as FoldConstantVectorArithmetic does, and rather than adding the constant shift to the work list instead only apply the transformation if it's already been folded into a constant, as if it's not we're going to loop endlessly. Additionally add missing NoOpaques to one of those transformations, which I noticed when writing the tests for this. Differential Revision: https://reviews.llvm.org/D26605 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287766 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
John Brawn
parent
fa8f01111c
commit
aae639e0bd
@ -2157,11 +2157,11 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
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if (N0.getOpcode() == ISD::SHL &&
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isConstantOrConstantVector(N1) &&
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isConstantOrConstantVector(N0.getOperand(1))) {
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isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
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isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
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SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
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AddToWorklist(C3.getNode());
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
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if (isConstantOrConstantVector(C3))
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
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}
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// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
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@ -4714,8 +4714,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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isConstantOrConstantVector(N1, /* No Opaques */ true) &&
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isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
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SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
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AddToWorklist(Shl.getNode());
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
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if (isConstantOrConstantVector(Shl))
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
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}
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if (N1C && !N1C->isOpaque())
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@ -3498,25 +3498,22 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
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EVT SVT = VT.getScalarType();
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SmallVector<SDValue, 4> Outputs;
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for (unsigned I = 0, E = BV1->getNumOperands(); I != E; ++I) {
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ConstantSDNode *V1 = dyn_cast<ConstantSDNode>(BV1->getOperand(I));
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ConstantSDNode *V2 = dyn_cast<ConstantSDNode>(BV2->getOperand(I));
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if (!V1 || !V2) // Not a constant, bail.
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return SDValue();
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if (V1->isOpaque() || V2->isOpaque())
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return SDValue();
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SDValue V1 = BV1->getOperand(I);
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SDValue V2 = BV2->getOperand(I);
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// Avoid BUILD_VECTOR nodes that perform implicit truncation.
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// FIXME: This is valid and could be handled by truncating the APInts.
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// FIXME: This is valid and could be handled by truncation.
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if (V1->getValueType(0) != SVT || V2->getValueType(0) != SVT)
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return SDValue();
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// Fold one vector element.
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std::pair<APInt, bool> Folded = FoldValue(Opcode, V1->getAPIntValue(),
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V2->getAPIntValue());
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if (!Folded.second)
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SDValue ScalarResult = getNode(Opcode, DL, SVT, V1, V2);
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// Scalar folding only succeeded if the result is a constant or UNDEF.
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if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant &&
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ScalarResult.getOpcode() != ISD::ConstantFP)
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return SDValue();
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Outputs.push_back(getConstant(Folded.first, DL, SVT));
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Outputs.push_back(ScalarResult);
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}
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assert(VT.getVectorNumElements() == Outputs.size() &&
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117
test/CodeGen/AArch64/dag-combine-mul-shl.ll
Normal file
117
test/CodeGen/AArch64/dag-combine-mul-shl.ll
Normal file
@ -0,0 +1,117 @@
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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; CHECK-LABEL: fn1_vector:
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; CHECK: adrp x[[BASE:[0-9]+]], .LCP
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; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
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; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
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; CHECK-NEXT: ret
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define <16 x i8> @fn1_vector(<16 x i8> %arg) {
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entry:
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%shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%mul = mul <16 x i8> %shl, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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ret <16 x i8> %mul
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}
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; CHECK-LABEL: fn2_vector:
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; CHECK: adrp x[[BASE:[0-9]+]], .LCP
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; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
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; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
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; CHECK-NEXT: ret
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define <16 x i8> @fn2_vector(<16 x i8> %arg) {
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entry:
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%mul = mul <16 x i8> %arg, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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ret <16 x i8> %shl
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}
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; CHECK-LABEL: fn1_vector_undef:
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; CHECK: adrp x[[BASE:[0-9]+]], .LCP
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; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
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; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
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; CHECK-NEXT: ret
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define <16 x i8> @fn1_vector_undef(<16 x i8> %arg) {
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entry:
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%shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%mul = mul <16 x i8> %shl, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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ret <16 x i8> %mul
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}
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; CHECK-LABEL: fn2_vector_undef:
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; CHECK: adrp x[[BASE:[0-9]+]], .LCP
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; CHECK-NEXT: ldr q[[NUM:[0-9]+]], [x[[BASE]],
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; CHECK-NEXT: mul v0.16b, v0.16b, v[[NUM]].16b
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; CHECK-NEXT: ret
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define <16 x i8> @fn2_vector_undef(<16 x i8> %arg) {
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entry:
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%mul = mul <16 x i8> %arg, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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ret <16 x i8> %shl
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}
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; CHECK-LABEL: fn1_scalar:
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; CHECK: mov w[[REG:[0-9]+]], #1664
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; CHECK-NEXT: mul w0, w0, w[[REG]]
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; CHECK-NEXT: ret
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define i32 @fn1_scalar(i32 %arg) {
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entry:
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%shl = shl i32 %arg, 7
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%mul = mul i32 %shl, 13
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ret i32 %mul
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}
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; CHECK-LABEL: fn2_scalar:
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; CHECK: mov w[[REG:[0-9]+]], #1664
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; CHECK-NEXT: mul w0, w0, w[[REG]]
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; CHECK-NEXT: ret
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define i32 @fn2_scalar(i32 %arg) {
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entry:
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%mul = mul i32 %arg, 13
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%shl = shl i32 %mul, 7
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ret i32 %shl
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}
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; CHECK-LABEL: fn1_scalar_undef:
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; CHECK: mov w0
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; CHECK-NEXT: ret
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define i32 @fn1_scalar_undef(i32 %arg) {
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entry:
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%shl = shl i32 %arg, 7
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%mul = mul i32 %shl, undef
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ret i32 %mul
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}
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; CHECK-LABEL: fn2_scalar_undef:
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; CHECK: mov w0
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; CHECK-NEXT: ret
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define i32 @fn2_scalar_undef(i32 %arg) {
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entry:
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%mul = mul i32 %arg, undef
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%shl = shl i32 %mul, 7
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ret i32 %shl
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}
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; CHECK-LABEL: fn1_scalar_opaque:
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; CHECK: mov w[[REG:[0-9]+]], #13
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; CHECK-NEXT: mul w[[REG]], w0, w[[REG]]
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; CHECK-NEXT: lsl w0, w[[REG]], #7
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; CHECK-NEXT: ret
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define i32 @fn1_scalar_opaque(i32 %arg) {
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entry:
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%bitcast = bitcast i32 13 to i32
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%shl = shl i32 %arg, 7
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%mul = mul i32 %shl, %bitcast
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ret i32 %mul
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}
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; CHECK-LABEL: fn2_scalar_opaque:
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; CHECK: mov w[[REG:[0-9]+]], #13
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; CHECK-NEXT: mul w[[REG]], w0, w[[REG]]
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; CHECK-NEXT: lsl w0, w[[REG]], #7
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; CHECK-NEXT: ret
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define i32 @fn2_scalar_opaque(i32 %arg) {
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entry:
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%bitcast = bitcast i32 13 to i32
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%mul = mul i32 %arg, %bitcast
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%shl = shl i32 %mul, 7
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ret i32 %shl
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}
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@ -26,15 +26,13 @@ define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: bar:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE-NEXT: psrlw $15, %xmm0
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; SSE-NEXT: psllw $5, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: bar:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0
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; AVX-NEXT: vpsllw $5, %xmm0, %xmm0
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%icmp = icmp eq <8 x i16> %a, %b
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